Document Outline

• ATCA-9405
• Regulatory Agency Warnings & Notices
• Contents
• About this Manual
  • Overview of Contents
  • Abbreviations
  • Conventions
  • Summary of Changes
• Introduction
  • 1.1 Overview
  • 1.2 Components and Features
  • 1.3 Functional Overview
  • 1.4 Additional Information
    • 1.4.1 Regulatory Compliance
    • 1.4.2 RoHS Compliance
    • 1.4.3 Notation
  • 1.5 Ordering Information
  • 1.6 Product Identification
• Setup
  • 2.1 Overview
  • 2.2 Electrostatic Discharge
  • 2.3 ATCA-9405 Circuit Board
    • 2.3.1 Switch Settings
      • 2.3.1.1 FPGA and CPLD/IPMC Switches
    • 2.3.2 Safety Critical Hot Spots
    • 2.3.3 Connector Pin Assignment
      • 2.3.3.1 Face Plate Connectors
      • 2.3.3.2 On-board Connectors
      • 2.3.3.3 Back Panel Connectors
    • 2.3.4 Debugging Headers
      • 2.3.4.1 IPMC Debug Console Header
      • 2.3.4.2 COP Header
      • 2.3.4.3 EJTAG Header
  • 2.4 ATCA-9405 Setup
    • 2.4.1 Power Requirements
    • 2.4.2 Environmental Considerations
    • 2.4.3 Hot Swap
  • 2.5 Troubleshooting
    • 2.5.1 Technical Support
    • 2.5.2 Product Repair
• Packet Processor
  • 3.1 Overview
  • 3.2 CN6880 Processor
  • 3.3 Cache
  • 3.4 System Memory
    • 3.4.1 Memory Interface
    • 3.4.2 Memory Socket
    • 3.4.3 Memory Modules
    • 3.4.4 Thermal Sensor
  • 3.5 Octeon U-Boot
    • 3.5.1 NVRAM
    • 3.5.2 Network Interfaces
  • 3.6 SerDes Configuration
  • 3.7 PCI Express Interface
  • 3.8 Ethernet Interface
    • 3.8.1 Front Panel Interface
    • 3.8.2 Base and Fabric Interface
  • 3.9 Interlaken Interface
  • 3.10 USB Interface
  • 3.11 UART Interface
  • 3.12 I2C Interface
  • 3.13 JTAG Interface
  • 3.14 Interrupts
    • 3.14.1 Packet Processor Interrupts
  • 3.15 Power Supply
  • 3.16 Cooling
• Service Processor
  • 4.1 Overview
  • 4.2 P2020 Processor
  • 4.3 Cache
  • 4.4 Main Memory
    • 4.4.1 Memory Interface
    • 4.4.2 Memory Socket
    • 4.4.3 Memory Modules
    • 4.4.4 Persistent Memory
    • 4.4.5 Thermal Sensor
  • 4.5 SP U-Boot
    • 4.5.1 Environment Variables
    • 4.5.2 Passing Parameter Set to the Operating System
    • 4.5.3 Dynamic Variables Set During the Boot Phase
    • 4.5.4 Variables for Controlling the Boot Progress
    • 4.5.5 Firmware Update
    • 4.5.6 Application/OS Boot
      • 4.5.6.1 Default Boot Sequences
    • 4.5.7 Memory/Address Map Initialization
      • 4.5.7.1 Address Map
  • 4.6 Local Bus
  • 4.7 SerDes Configuration
  • 4.8 PCI Express Interface
  • 4.9 Ethernet Interface
    • 4.9.1 Front Panel Interface
    • 4.9.2 Base and Fabric Interface
  • 4.10 SPI Interface
    • 4.10.1 Boot Flash
    • 4.10.2 Boot Flash Selection
  • 4.11 USB Interface
    • 4.11.1 USB Connector
    • 4.11.2 e-USB Flash Drive
  • 4.12 UART Interface
  • 4.13 I2C Interface
    • 4.13.1 Real Time Clock (RTC)
  • 4.14 JTAG Interface
  • 4.15 Interrupts
    • 4.15.1 Service Processor Interrupts
  • 4.16 Cooling
• Ethernet Infrastructure
  • 5.1 Overview
  • 5.2 Ethernet Switch
    • 5.2.1 Port Configuration
    • 5.2.2 Two-Wire Serial Interface
    • 5.2.3 Switch Management Interface
    • 5.2.4 PHY Management Interface
  • 5.3 Base Interface
  • 5.4 Fabric Interface
  • 5.5 Update Channel
  • 5.6 Serial Redirection
• Service Infrastructure
  • 6.1 Overview
  • 6.2 Port Configuration
  • 6.3 Hot Plug Support
    • 6.3.1 Serial Hot Plug Controller
  • 6.4 I2C Slave Interface
  • 6.5 JTAG Support
  • 6.6 Lane Status
• Mezzanine Module
  • 7.1 Overview
• Intelligent Peripheral Management Controller
  • 8.1 Overview
  • 8.2 Functional Overview
  • 8.3 Firmware Architecture
  • 8.4 HPM.1 Components
    • 8.4.1 FPGA Firmware Upgrade
    • 8.4.2 Payload Firmware Upgrade
    • 8.4.3 IPMC Firmware Upgrade
    • 8.4.4 Manual Rollback
    • 8.4.5 Retrieving Versioning Information
  • 8.5 Sensors
    • 8.5.1 Firmware Progress, OS Boot, and Boot Error Sensor
    • 8.5.2 Boot Bank Supervision Sensor
    • 8.5.3 POST Results Sensor
    • 8.5.4 Power Good Sensor
    • 8.5.5 Power Interface Sensors
    • 8.5.6 Reset Cause Sensor
    • 8.5.7 Presence Sensors
    • 8.5.8 Voltage and Temperature Sensors
  • 8.6 POST
  • 8.7 FRU Inventory
    • 8.7.1 MAC Address FRU OEM records
  • 8.8 Reset and Power Domains
  • 8.9 Power Management
  • 8.10 U-Boot Boot Configuration Parameters
  • 8.11 Asynchronous Event Notification
  • 8.12 Serial Line Selection
  • 8.13 Built-in Terminal Server
    • 8.13.1 Evaluating the Version of the Telnet Server Firmware
    • 8.13.2 Establishing a Telnet Session
  • 8.14 Fail Safe Logic and Watchdog Support
    • 8.14.1 SP BMC Watchdog
  • 8.15 Payload Interface
  • 8.16 Payload Boot Bank Selection
  • 8.17 Settable Graceful Shutdown Timeout
  • 8.18 FPGA Health Check
  • 8.19 Local System Event Log (SEL)
  • 8.20 IPMI Hardware Watchdog
  • 8.21 Artesyn OEM Command Set
    • 8.21.1 Set Serial Output Command
    • 8.21.2 Get Serial Output Command
    • 8.21.3 Set Feature Configuration
    • 8.21.4 Get Feature Configuration
• A Related Documentation
  • A.1 Artesyn Embedded Technologies - Embedded Computing Documentation
• Safety Notes
• Sicherheitshinweise