BECKHOFF BK4000 - Manual (Page 19)

Basic information
BK4000 19
1) The data widths are only supported from Firmware version 3.20 and
higher by the interfaces of the PLC and from driver version 2.0 by the PC
card.
Remark: In InterBus master interfaces with firmware versions less than 4.0, the pe-
ripheral data block of a bus coupler can only be placed in the process
image as a coherent block with one base address. All following data of the
block is assigned to the subsequent addresses.
Register expansion The differing length of the bus coupler is realised by a rigister expansion.
The number of additional registers is switched by the internal micro pro-
cessor. The length is determined after power-on or after a reset and is
written into a register expansion module as a numeric value. A change in
the length is not possible without interrupting the exchange of data on the
InterBus. The BK4000 must be restarted by means of a reset. The master
must be reconfigured to the new length. In the auto configuration mode of
some InterBus masters, the master starts even after the length of individual
slaves has been modified if this does not result in any overlapping of
addresses.
Run times and reaction times
Controller / master Transfer of the signals from the input into the controller and from the cont-
roller to the outputs requires a run time. This is composed of various porti-
ons, i.e. transfer from the controller to the master; transfer via the InterBus
and transfer from the bus coupler to the outputs. It applies conversly in the
return direction.
Refer to the master manufacturer’s data for details of the reaction time
from the controller to the Master. The newly transferred data does not ac-
quire validity until one cycle has been transferred completely.
The reaction time TIBS on the InterBus is composed of the following. The
constants SW, M, N and TBIT constitute the sum of the cycle time in ms. In
the worst case, the reaction time is 2 x cycle time because the data does
not acquire validity until after the end of the cycle.
TIBS = ( SW + (13 * ( 6 + N ) + 1,5 * M ) x TBIT ) * 2
SW = 0.2 ms
M = Number of bus couplers
N = Number of effective byte lengths
TBIT = 0.002 ms
Pay attention to the number of bytes and not the word length in the calcula-
tion of the times.
Note:
Pay attention to particular delays in the event of transmission errors.The
InterBus requires 5 cycle times until the next valid data can be exchanged.