BECKHOFF EtherCAT Registers Section II - Manual (Page 17)

Address Space Overview
Slave Controller – Register Description II-5
1.1 Scope of Section II
Section II contains detailed information about all ESC registers. This section is also common for all
Beckhoff ESCs, thus registers, register bits, or features are described which might not be available in
a specific ESC. Refer to the register overview in Section III of a specific ESC to find out which
registers are available. Additionally, refer to the feature details overview in Section III of a specific ESC
to find out which features are available.
The following Beckhoff ESCs are covered by Section II:

ET1200-0003

ET1100-0003

EtherCAT IP Core for Altera FPGAs (V2.4.3 / V3.0.2)

EtherCAT IP Core for Xilinx FPGAs (V2.04d / V3.00c)

ESC20 (Build 22)
1.2 Reserved Registers/Reserved Register Bits
Reserved registers must not be written, reserved register bits have to be written as 0. Read values of
reserved registers or register bits have to be ignored. Reserved registers or register bits initialized by
EEPROM values have to be initialized with 0.
Reserved EEPROM words of the ESC configuration area have to be 0.