IBASE MI941 - Manual (Page 29)

BIOS SETUP
MI941 User’s Manual 25
Adjacent Cache-Line Prefetch
The Adjacent Cache-Line Prefetch mechanism, like automatic hardware
prefetch, operates without programmer intervention. When enabled
through the BIOS, two 64-byte cache lines are fetched into a 128-byte
sector, regardless of whether the additional cache line has been
requested or not. In applications with relatively poor spatial locality, the
cache miss ratio is higher. A cache miss on an Intel® Pentium® 4
processor-based system (with adjacent sector prefetch enabled) brings in
128 bytes, leading to higher bus utilization (assuming that the
application didn’t need the other 64 bytes). When adjacent sector
prefetch is disabled, an Intel® P entium® 4 processor-based system only
fetches 64 bytes. The other 64 bytes of the sector in the last-level cache
are not used unless the application explicitly issues a load to that address.
Disabling adjacent sector prefetch on Intel® Pentium® 4
processor-based systems can reduce bus traffic.