Sundance SMT395E - Manual (Page 3)

Version 2.1 Page 3 of 30 SMT395Q User Manual
Table of Contents
Revision History ....................................................................................................... 2
Contacting Sundance............................................................................................... 4
Notational Conventions ........................................................................................... 5
C60 ......................................................................................................................... 5
Register Descriptions .............................................................................................. 5
Outline Description .................................................................................................. 6
Block Diagram .......................................................................................................... 7
Architecture Description.......................................................................................... 8
TMS320C6416T ......................................................................................................... 9
Boot Mode............................................................................................................. 10
Flash Boot........................................................................................................ 10
EMIF Control Registers......................................................................................... 11
SDRAM .................................................................................................................... 12
FLASH ..................................................................................................................... 12
FLASH Paging ................................................................................................. 12
Virtex-II Pro FPGA .................................................................................................. 13
External Clock......................................................................................................... 13
Version control ....................................................................................................... 13
Reprogramming the firmware and boot code ...................................................... 13
FPGA resources ..................................................................................................... 14
Interrupts............................................................................................................... 14
Communication ports ............................................................................................ 14
SDB ...................................................................................................................... 14
SDB Clock selection .......................................................................................... 14
RSL ....................................................................................................................... 14
Global bus............................................................................................................. 14
CONFIG & NMI ..................................................................................................... 14
Timer..................................................................................................................... 14
IIOF interrupt......................................................................................................... 15
LED ....................................................................................................................... 15
TTL ....................................................................................................................... 15