Sundance SMT398VP - Manual (Page 18)

4.1.4.12. DIP Switches
• Two four-position DIP switches are connected to the CPLD to provide
control over the selection of the configuration bitstream source, and a special
reset feature called “TIM Confign”. (See
Bottom View)
SW1 pos 4 TIM Confign
ON ENABLED
OFF DISABLED
Table 2: DIP switch for special reset feature
SW1 pos 3,2, 1 JPC3 JPC2 JPC1
C0P ON ON ON
C3P OFF OFF OFF
PROM OFF OFF ON
Table 3: DIP switch for the selection of the configuration bitstream source
4.1.4.13. Clocking scheme
The SMT398VP module provides a 50MHz LVTTL clock and a clock synthesiser.
• 50 MHz LVTTL oscillator: Main system clock. Clocks the CPLD and the
FPGA. Can be input in a DCM.
•
ICS clock synthesizer 8442 , used to generate any frequencies between 31.25
MHz up to 700MHz with a jitter lower than 40ps required for the Rocket I/O
transceiver REFCLK input.
A 25MHz Crystal is used on this board as the input to the clock synthesizer’s
on-chip oscillator.
The TEST output from the clock synthesizer is not available on a pin of the
FPGA but can be observed from the board directly from hole T1 (See
Figure
5: Top View )
The clock synthesiser is programmed by the FPGA.
The clock synthesiser’s differential LVDS outputs are both available on pins
of the FPGA as pre
Figure 4: Clocking distribution diagram.
Document No.
S M T 3 9 8 V P - D 0 0 0 0 5 8 H - g u i d e . d o c
Revision
2 . 4 . 2
Date
0 8 / 0 2 / 0 7
Page 18 of 34