Linx Technologies TXM-xxx-ES - Manual (Page 7)

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Theory of Operation
The ES Series FM / FSK transmitter is capable of generating 1mW of
output power into a 50-ohm load while suppressing harmonics and
spurious emissions to within legal limits. The transmitter is comprised
of a VCO and a crystal-controlled frequency synthesizer. The frequency
synthesizer, referenced to a precision crystal, locks the VCO to achieve a
high-Q, low phase-noise oscillator.
The transmitter operates by directly modulating the crystal with the
baseband signal present on the DATA line. Pulling the crystal in this
manner achieves the desired deviation and linearity. If the transmitter’s VCO
were modulated, the frequency synthesizer would track out much of the
deviation within the bandwidth of the loop filter (this is a common limitation
of most synthesized FM transmitters). The carrier is then amplified and
filtered before being output on the 50-ohm ANT line.
The frequency of the Divided Clock output is determined by the state of the
Clock Frequency Selection line. A low on the Select line generates a signal
on the clock output that is the center frequency divided by 256, a high will
be the center frequency divided by 1,024.
Using the Divided Clock Output (/CLK)
When the ES is used with a microcontroller, the divided clock output (/
CLK) saves cost and space by eliminating the need for a crystal or other
frequency reference for the microprocessor. This line is an open collector
output, so an external pull-up resistor (R
L
) should be connected between
this line and the positive supply voltage. The value of R
L
is calculated using
two factors.
1. Determine the clock frequency (f
CLKOUT
). If /CLK SE is open, the /CLK
output is the TX center frequency (in MHz) divided by 1,024; if /CLK
SEL is grounded, it is divided by 256.
2. Determine the load capacitance of the PCB plus the microcontroller’s
input capacitance (C
LD
in pF).
Using these two factors, the value of R
L
is calculated:
“/256” R
L
= 1000/(f
CLKOUT
*8* C
LD
) “/1024” R
L
= 1000/(f
CLKOUT
*8* C
LD
)
Example: Example:
For /256: 1000/((916.48/256)x8x5)=6.98k Ω For /1024: 1000/((916.48/1024)x8x5)=27.9kΩ
Using LADJ
The transmitter’s output power can be externally adjusted by approximately
65dBm using the LADJ line. This eliminates the need for external
attenuation and allows the transmitter’s power to be easily adjusted for
range control, lower power consumption, or to meet legal requirements.
When the LADJ line is open, the output power is at its maximum and the
transmitter draws 7mA typically. When LADJ is at 0V, the output power is at
its minimum and the transmitter draws 3mA typically.
The transmit power is set to a particular level by placing a resistor from the
LADJ line to ground. This resistor works in combination with an internal
supply pull-up to create a voltage divider. This voltage level sets the power
amplifier’s gain and the output power. Figure 5 shows typical resistor values
and corresponding attenuation levels.
The LADJ line is very useful during FCC testing to compensate for antenna
gain or other product-specific issues that may cause the output power to
exceed legal limits. Often it is wise to connect the LADJ line to a variable
resistor so that the test lab can precisely adjust the output power to the
maximum threshold allowed by law. The resistor’s value can then be noted
and a fixed resistor substituted for final testing. Even in designs where
attenuation is not anticipated, it is a good idea to place a resistor pad
connected to LADJ so that it can be used if needed.
For more sophisticated designs, LADJ may also be controlled by a DAC
or digital potentiometer to allow precise and digitally variable output power
control.
In any case where the voltage on the LADJ line may fall below 1.5VDC,
a low value ceramic capacitor (200 to 4,700pF) must be placed from the
module’s power supply to the LADJ pin. This is necessary to meet the
module’s minimum enable voltage at start-up.