Encoder typical application, Decoder typical application – Linx Technologies LICAL-EDC-DS User Manual
Page 10
–
–
–
–
14
15
Encoder Typical Application
Figure 15 shows a circuit using the DS Series configured as a Holtek
®
encoder. This configuration matches the Linx OEM products.
The P_SEL line is set to Holtek
®
data (pulling it to Vcc selects the Serial
protocol. The E/D_SEL line is pulled high to place the DS into Encoder
Mode. The D_CFG is set so that a high on a data line is transmitted as a
one bit and a low on the line is transmitted as an open bit. The A_CFG0
and A_CFG1 lines are set to give a high on an address line as an open bit
and a low as a zero bit.
The data lines are bi-state, so they have to be high or low. They cannot be
floating. Resistors to ground pull the lines low and buttons pull the lines
high when pressed. Diodes are used to pull TE high when any button is
pressed without activating any other line. This way, pushing any button
causes the encoder to start outputting data.
The address lines are bi-state, so they have to be high or low. They cannot
be floating. Resistors pull the lines high and DIP switches pull them low.
R4 100k
S0
S1
S2
S3
S4
S5
S6
S7
VCC
R5 100k
R6 100k
R7 100k
R0 100k
R3 100k
R2 100k
R1 100k
D0
D1
D2
D3
D4
D5
D6
D7
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
1
2
3
20
19
18
4
5
6
17
16
15
7
8
9
14
13
12
10
11
SW1
R13
100k
R14
100k
R15
100k
R16
100k
R17
100k
R12
100k
R11
100k
R10
100k
R9
100k
R8
100k
VCC
GND
VCC
E/D_SEL
R18
100k
GND
8
GND
P_SEL
1
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
GND
D6
9
D7
10
11
D_CFG
12
A_CFG0
13
A_CFG1
14
A0
15
A1
16
A2
17
A3
18
GND
19
VCC
20
A4
21
A5
22
A6
23
A7
24
A8
25
A9
26
TE/DI
27
VT/DO
28
U1
LICAL-EDC-DS001
VCC
TX_DATA
GND
GND
GND
VCC
VCC
VCC
Holtek
Serial
GND
Figure 15: DS Series Typical Application as an Encoder
Decoder Typical Application
Figure 16 shows a circuit using the DS Series configured as a Holtek
®
decoder. This configuration matches the Linx OEM products.
The P_SEL line is set to Holtek
®
data. The E/D_SEL line is pulled low to
place the DS into decoder mode. The A_CFG0 and A_CFG1 lines are set
to give a high on an address line as an open bit and a low as a zero bit.
The address lines are bi-state, so they have to be high or low. They cannot
be floating. Resistors are used to pull the lines high and DIP switches pull
them low when on.
Pulling the P_SEL line to Vcc enables the serial protocol. The rest of the
application circuit is the same, though the D_CFG, A_CFG0 and A_CFG1
lines are ignored and can be tied to Vcc or GND with no affect on the
operation. They should not be left open.
U1
P_SEL
1
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
GND
8
D6
9
D7
10
E/D_SEL
11
D_CFG
12
A_CFG0
13
A_CFG1
14
A0
15
A1
16
A2
17
A3
18
GND
19
VCC
20
A4
21
A5
22
A6
23
A7
24
A8
25
A9
26
TE/DI
27
VT/DO
28
LICAL-EDC-DS001
VCC
RX_DATA
GND
GND
GND
VCC
GND
D0
D1
D2
D3
D4
D5
D6
D7
VT
1
2
3
20
19
18
4
5
6
17
16
15
7
8
9
14
13
12
10
11
SW1
R13
100k
R14
100k
R15
100k
R16
100k
R17
100k
R12
100k
R11
100k
R10
100k
R9
100k
R8
100k
VCC
GND
VCC
GND
VCC
Holtek
Serial
GND
Figure 16: DS Series Typical Application as a Decoder