Linx Technologies LICAL-EDC-DS - Manual (Page 8)

– – – – 10 11
Example packets are shown in Figure 10 with all lines set in a specific state.
Figure 11 shows the timings associated with the Holtek ® protocol.
Input Type Selection
The DS Series is designed to be operable with Holtek ® encoders and
decoders, but there is one key condition. The Holtek ® encoders and
decoders have tri-state input lines but the DS has bi-state lines. Tri-state
inputs are connected to ground for zero bits, V
CC
for one bits, or left
unconnected for open bits. Since the DS cannot match this operation
the D_CFG, A_CFG0 and A_CFG1 lines are provided to select the desired
interpretation. The settings must match on both ends.
Pulling D_CFG high configures the data inputs as one and zero. A high on
a data line is interpreted as a one bit and a low on the line is interpreted
as a zero bit. Pulling D_CFG low configures the data inputs as one and
open. A high on a data line is interpreted as a one bit and a low on the line
is interpreted as an open bit. The decoder outputs open data bits as logic
low. This is shown in Figure 12.
A_CFG0 and A_CFG1 are used to select the bit type for the address lines.
These are shown in Figure 13.
Products that need to operate with the older Holtek products need to
set these configuration lines according to how the Holtek
® encoders and
decoders are implemented in the product.
D_CFG Configuration
Configuration Bit Interpretation
D_CFG High Low
0 One Open
1 One Zero
A_CFGO and A_CFG1 Configuration
Configuration Bit Interpretation
A_CFG1 A_CFG0 High Low
0 0 One Zero
0 1 One Open
1 0 Open Zero
1 1 One Zero
Figure 12: D_CFG Configuration
Figure 13: A_CFG0 and A_CFG1 Configuration
Check Check
< 1 Word
3 Words Transmitted Continuously
3 Words
Decoder
Data Out
Decoder VT
Encoder
Data Out
Encoder
Transmit
Enable
2 Words
SYNC BITS
A&D BITS
PULLED TO
VCC
ADDRESS BITS DATA BITS
A&D BITS
OPEN
A&D Bits
PULLED TO
GND
SYNC
PERIOD SYNC BITS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 D0 D1 D2 D3 D4 D5 D6 D7
Figure 10: Holtek ® Protocol Timing
Figure 11: DS Series Timing