Linx Technologies LICAL-EDC-DS - Manual (Page 9)

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Serial Data and Packet Structure
The serial protocol encodes the address and data lines as binary bits that
follow logic low and logic high voltage levels. The logic states of each line
are recorded and placed into bytes. A checksum is calculated on the bytes
and appended to the end of the packet. A preamble and a noise filter are
added to the front. The packet is shown in Figure 14.
The bytes are output in serial fashion at 4,800bps. The DS outputs the
packet twice, with the second packet being the logical inversion of the first.
This ensures that the duty cycle of the data is always 50%. Adding in the
blanking period between packets lowers the duty cycle. This is important
for FCC certification where the transmitter output power level is a function
of the data duty cycle.
This protocol only uses binary states, so the D_CFG, A_CFG0 and A_CFG1
lines are ignored.
The serial protocol is much more immune to bit edge jitter than the Holtek ®
protocol. This gives much better range and performance within that range.
This also gives the DS better immunity to noise from motors, switching
power supplies, high current drivers and other noise sources.
This protocol updates the data line states on every packet. This, combined
with a faster data rate, give the serial protocol a much faster response time
than the Holtek
® protocol (36.5ms typical compared to 135ms).
The serial protocol compares two packets as part of the data validation,
but also includes a timer that keeps the outputs stable in the case of
mismatched packets. This prevents the outputs from turning off at the
loss of one packet or when a data line is toggled while another one is
active. This helps prevent chattering of relays and other electro-mechanical
devices that are not designed for rapid switching. The outputs turn off after
130ms with no valid data.
0 1010 1010 1 0 1010 1010 1 0 aa00 0000 1 0 dddd dddd 1 0 1001 1001 1 0 aaaa aaaa 1 0 cccc cccc 1
2 Byte Preamble
1ms Low 1ms High
Sync Byte Addr. Bits 0-7 Addr. Bits 8-9 Data Bits 0-7 Checksum Noise Filter
Figure 14: Serial Protocol Packet Structure
Operation with the Holtek ® HT640 and HT658
The DS is fully compatible with the Holtek ® HT640 encoder and the HT658,
and HT648L decoders. The primary operational difference is that the DS
Series has bi-state address lines (high or low) while the Holtek
® parts have
tri-state lines (high, low or floating). Since these are distinct states for the
Holtek
® parts, three configuration lines are used to select how the inputs
are interpreted. This accommodates most applications using the Holtek ®
parts.
The states of the A_CFG0 and A_CFG1 lines determine how the DS Series
interprets the states of its address lines. These lines allow for the use of any
two of Holtek
® ’s three states at a time. The states are outlined in Figure 13.
The state of the D_CFG line determines how the DS Series interprets the
states of its data lines when in Encoder Mode. This allows for the use of
any two of Holtek
®’ s three states at a time. The states are outlined in Figure
12.
While the DS Series is not fully compatible with the Holtek ® parts because
of the lack of tri-state lines, the use of the configuration lines allows most
applications to make a seamless transition to the DS.
Note: Contact Linx for compatability with other Holtek ® encoder/
decoder products.