Avago Technologies LSI53C1010 - Manual (Page 107)

Instruction Descriptions 3-67
Field(s) This command has the following fields:
Register
Definition(s) The information listed below describes the DBC and DSPS registers.
Description The Store instruction is more efficient than the Move Memory instruction
when moving data from an internal register of the chip to memory. It is
a two Dword instruction. This instruction may be used to move up to
Figure 3.20 STORE Format
31 29 28 27 26 25 24 23 22 16 15 3 2 0
DCMD Register DBC Register
Instr Type
DSA
Relative
R
No
Flush
Load/Store R Register Address R Byte Count
1 1 1 x 0 0 x 0 0 x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x
31 0
DSPS Register
Destination Address/DSA Offset
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Instruction
Type Load/Store.
DSA Relative Indicates source address location.
0 - DSPS contains actual address of data to load
1 - DSPS contains a 24-bit offset value that is added to the
DSA to determine the source address
No Flush When this bit is cleared, the prefetch buffer is flushed during
the Store instruction. When set, the prefetch buffer is not
flushed automatically on a Store instruction.
Load/Store This field defines whether the instruction will be executed as a
Load or a Store.
0 - Store instruction
1 - Load instruction
Reg Addr These bits select the register to load within the chip operating
register set.
Byte Count A 3-bit number indicating the number of bytes to transfer.
Destination
Addr Actual address (or offset from the DSA) of the destination
address.