Avago Technologies LSI53C1010 - Manual (Page 112)

3-72 The SCSI SCRIPTS Processor Instruction Set
Register
Definition(s) The information listed below describes the DBC and DSPS registers.
Description The initiator waits to be reselected by a previously selected target device.
If the chip is responding to a previous reselection, it fetches and executes
the next instruction. If the chip has already responded to reselection, it
immediately fetches the next instruction. If the operation completes as
expected, the next instruction is fetched and executed by the SCRIPTS
processor. However, if the chip is selected, then the alternate jump
address should contain the address of a selection algorithm. Target
instructions must include a WAIT in the address. That instruction's
alternate address is the error recovery algorithm (for initiator role–
reselect). The chip can determine exactly what happened and transfer
control to the appropriate SCSI SCRIPTS algorithm. If the SIGP bit in the
ISTAT register is set by the host processor, the chip will also fetch the
instruction at the alternate address. This allows the driver program to
schedule another I/O instead of waiting for the reselection to complete.
This driver code activity is illustrated in
Figure 3.24 .
Opcode Wait Reselect.
Relative Mode Indicates that the 24-bit address is an offset from the current
program counter.
Destination
Address Specifies the memory address of the next instruction to fetch if
a reselection occurs or the SIGP bit is set by the host
processor.