Epson S1D13705 User Manual

Page 71

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Epson Research and Development

Page 65

Vancouver Design Center

Hardware Functional Specification

S1D13705

Issue Date: 02/02/01

X27A-A-001-10

Figure 8-1: Screen-Register Relationship, Split Screen

Consider an example where REG[13h], REG[12] = 0CEh for a 320x240 display system.
The upper 207 lines (CEh + 1) of the panel show an image from the Screen 1 Start Word
Address. The remaining 33 lines show an image from the Screen 2 Start Word Address.

bits 7-0

LUT Address Bits [7:0]
These 8 bits control a pointer into the Look-Up Tables (LUT). The S1D13705 has three
256-position, 4-bit wide LUTs, one for each of red, green, and blue – refer to Section 11,
“Look-Up Table Architecture” on page 71 f
or details.

This register selects which LUT entry is read/write accessible through the LUT Data Reg-
ister (REG[17h]). Writing the LUT Address Register automatically sets the pointer to the
Red LUT. Accesses to the LUT Data Register automatically increment the pointer.

For example, writing a value 03h into the LUT Address Register sets the pointer to R[3].
A subsequent access to the LUT Data Register accesses R[3] and moves the pointer onto
G[3]. Subsequent accesses to the LUT Data Register move the pointer onto B[3], R[4],
G[4], B[4], R[5], etc.

Note

The RGB data is inserted into the LUT after the Blue data is written, i.e. all three colors
must be written before the LUT is updated.

REG[15h] Look-Up Table Address Register
Address = 1FFF5h

Read/Write

LUT Address

Bit 7

LUT Address

Bit 6

LUT Address

Bit 5

LUT Address

Bit 4

LUT Address

Bit 3

LUT Address

Bit 2

LUT Address

Bit 1

LUT Address

Bit 0

Line 0

Line 1

(REG[0Dh], REG[0Ch]) Words

Line 0 Last Pixel Address + REG[11h] Words

Line 0 Last Pixel Address=((REG[0Dh], REG[0Ch]) +

(8(REG[04h]+1)

×

BPP/16))

8(REG[04h]+1) Pixels

Virtual Image

REG[11h] Words

Line=(REG[13h], REG[12h])

((REG[06h], REG[05])+1) Lines

Image 1

Image 2

(REG[0Fh], REG[0Eh]) Words

Where:
(REG[0Dh], REG[0Ch]) is the Screen 1 Start Word Address
BPP is Bits-per-Pixel as set by REG[02h] bits 7:6
REG[11h] is the Address Pitch Adjustment in Words
(REG[0Fh], REG[0Eh]) is the Screen 2 Start Word Address
(REG[13h], REG[12h]) is the Screen 1 Vertical Size
(REG[06h], REG[05h]) is the Vertical Panel Size

Words

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