Epson S1D13705 User Manual
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S1D13705 Embedded Memory LCD Controller
S1D13705
TECHNICAL MANUAL
Document No. X27A-Q-001-04
Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
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Table of contents
Document Outline
- S1D13705 TECHNICAL MANUAL
- Product Brief
- Hardware Functional Specification
- Table of Contents
- List of Tables
- List of Figures
- 1 Introduction
- 2 Features
- 3 Typical System Implementation Diagrams
- Figure 31: Typical System Diagram (SH-4 Bus)
- Figure 32: Typical System Diagram (SH-3 Bus)
- Figure 33: Typical System Diagram (M68K #1 Bus)
- Figure 34: Typical System Diagram (M68K #2 Bus)
- Figure 35: Typical System Diagram (Generic #1 Bus)
- Figure 36: Typical System Diagram (Generic #2 Bus - e.g. ISA Bus)
- 4 Functional Block Diagram
- 5 Pins
- 6 D.C. Characteristics
- 7 A.C. Characteristics
- 7.1 Bus Interface Timing
- 7.2 Clock Input Requirements
- 7.3 Display Interface
- 7.3.1 Power On/Reset Timing
- 7.3.2 Power Down/Up Timing
- 7.3.3 Single Monochrome 4-Bit Panel Timing
- 7.3.4 Single Monochrome 8-Bit Panel Timing
- 7.3.5 Single Color 4-Bit Panel Timing
- 7.3.6 Single Color 8-Bit Panel Timing (Format 1)
- 7.3.7 Single Color 8-Bit Panel Timing (Format 2)
- 7.3.8 Dual Monochrome 8-Bit Panel Timing
- 7.3.9 Dual Color 8-Bit Panel Timing
- 7.3.10 9/12-Bit TFT/D-TFD Panel Timing
- 8 Registers
- 8.1 Register Mapping
- 8.2 Register Descriptions
- Table 81: Panel Data Format
- Table 82: Gray Scale/Color Mode Selection
- Table 83: High Performance Selection
- Table 84: Inverse Video Mode Select Options
- Table 85: Hardware Power Save/GPIO0 Operation
- Table 86: Software Power Save Mode Selection
- Figure 81: Screen-Register Relationship, Split Screen
- Table 87: Selection of SwivelView Mode
- Table 88: Selection of PCLK and MCLK in SwivelView Mode
- 9 Frame Rate Calculation
- 10 Display Data Formats
- 11 Look-Up Table Architecture
- 12 SwivelView™
- 13 Power Save Modes
- 14 Mechanical Data
- 15 Sales and Technical Support
- Programming Notes and Examples
- Table of Contents
- List of Tables
- List of Figures
- 1 Introduction
- 2 Initialization
- 3 Memory Models
- 4 Look-Up Table (LUT)
- 5 Advanced Techniques
- 6 LCD Power Sequencing and Power Save Modes
- 7 Hardware Rotation
- 8 Identifying the S1D13705
- 9 Hardware Abstraction Layer (HAL)
- 10 Sample Code
- Register Summary
- 13705CFG Configuration Program
- 13705SHOW Demonstration Program
- 13705SPLT Display Utility
- 13705VIRT Display Utility
- 13705PLAY Diagnostic Utility
- 13705BMP Demonstration Program
- 13705PWR Power Save Utility
- Windows® CE 2.x Display Drivers
- Wind River WindML v2.0 Display Drivers
- Wind River WindML v2.0 DISPLAY DRIVERS
- Building a WindML v2.0 Display Driver
- 1. Create a working directory and unzip the WindML display driver into it.
- 2. Configure for the target execution model.
- 3. Build a boot ROM image.
- 4. Create a bootable disk (in drive A:).
- 5. If necessary, generate a new mode0.h configuration file.
- 6. Build the WindML v2.0 library.
- 7. Open the S1D13705 workspace.
- 8. Add support for single line comments.
- 9. Compile the VxWorks image.
- 10. Copy the VxWorks file to the diskette.
- 11. Start the VxWorks demo.
- Building a WindML v2.0 Display Driver
- Wind River WindML v2.0 DISPLAY DRIVERS
- Wind River UGL v1.2 Display Drivers
- Wind River UGL v1.2 Display Drivers
- Building a UGL v1.2 Display Driver
- 1. Create a working directory and unzip the UGL display driver into it.
- 2. Configure for the target execution model.
- 3. Build a boot ROM image.
- 4. Create a bootable disk (in drive A:).
- 5. If necessary, generate a new mode0.h configuration file.
- 6. Open the S1D13705 workspace.
- 7. Add support for single line comments.
- 8. Compile the VxWorks image.
- 9. Copy the VxWorks file to the diskette.
- 10. Start the VxWorks demo.
- Building a UGL v1.2 Display Driver
- Wind River UGL v1.2 Display Drivers
- Linux Console Driver
- Linux Console Driver
- Building the Console Driver for Linux Kernel 2.2.x
- Building the Console Driver for Linux Kernel 2.4.x
- 1. Acquire the Linux kernel source code.
- 2. Unzip the console driver files.
- 3. Copy the console driver files to the build directory. Make the directory /usr/src/linux/driver...
- 4. Modify s1d13705.h
- 5. Configure the video options.
- 6. Compile and install the kernel
- 7. Boot to the Linux operating system
- Linux Console Driver
- QNX Photon v2.0 Display Driver
- S1D13XXX 32-Bit Windows Device Driver Installation Guide
- S5U13705B00C Rev. 1.0 ISA Bus Evaluation Board User Manual
- Table of Contents
- List of Tables
- List of Figures
- 1 Introduction
- 2 Installation and Configuration
- 3 LCD Interface Pin Mapping
- 4 CPU/Bus Interface Connector Pinouts
- 5 Host Bus Interface Pin Mapping
- 6 Technical Description
- 6.1 Embedded Memory Support
- 6.2 ISA Bus Support
- 6.3 Non-ISA Bus Support
- 6.4 Decoding Logic
- 6.5 Clock Input Support
- 6.6 LCD Panel Voltage Setting
- 6.7 Monochrome LCD Panel Support
- 6.8 Color Passive LCD Panel Support
- 6.9 Color TFT/D-TFD LCD Panel Support
- 6.10 Power Save Modes
- 6.11 Adjustable LCD Panel Negative Power Supply
- 6.12 Adjustable LCD Panel Positive Power Supply
- 6.13 CPU/Bus Interface Header Strips
- 7 Parts List
- 8 Schematic Diagrams
- S5U13705B00C Rev. 2.0 Evaluation Board User Manual
- Table of Contents
- List of Tables
- List of Figures
- 1 Introduction
- 2 Features
- 3 Installation and Configuration
- 3.1 Configuration DIP Switches
- 3.2 Configuration Jumpers
- Table 32: Jumper Summary
- Figure 32: Configuration Jumper (JP1) Location
- Figure 33: Configuration Jumper (JP2) Location
- Figure 34: Configuration Jumper (JP3) Location
- Figure 35: Configuration Jumper (JP4) Location
- Figure 36: Configuration Jumper (JP5) Location
- Figure 37: Configuration Jumper (JP6) Location
- Figure 38: Configuration Jumper (JP7) Location
- 4 CPU Interface
- 5 LCD Interface Pin Mapping
- 6 Technical Description
- 7 Software
- 8 References
- 9 Parts List
- 10 Schematics
- 11 Board Layout
- 12 Technical Support
- Windows® CE 3.x Display Drivers
- Interfacing to the Toshiba MIPS TMPR3912 Microprocessor
- Table of Contents
- List of Tables
- List of Figures
- 1 Introduction
- 2 Interfacing to the TMPR3912
- 3 S1D13705 Host Bus Interface
- 4 Direct Connection to the Toshiba TMPR3912
- 5 Using the ITE IT8368E PC Card Buffer
- 6 Software
- 7 Technical Support
- S1D13705 Power Consumption
- Interfacing to the Motorola ‘Dragonball’ Family of Microprocessors
- Document Number: X27A-G-007-04
- Table of Contents
- List of Tables
- List of Figures
- 1 Introduction
- 2 Interfacing to the MC68328
- 3 Interfacing to the MC68EZ328
- 4 Interfacing to the MC68VZ328
- 5 Software
- 6 References
- 7 Technical Support
- Interfacing to the NEC VR4102/VR4111 Microprocessor
- Interfacing to the PC Card Bus
- Interfacing to the Motorola MPC821 Microprocessor
- Document Number: X27A-G-010-02
- Table of Contents
- List of Tables
- List of Figures
- 1 Introduction
- 2 Interfacing to the MPC821
- 3 S1D13705 Host Bus Interface
- 4 MPC821 to S1D13705 Interface
- 5 Software
- 6 References
- 7 Technical Support
- Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
- Interfacing to the Philips MIPS PR31500/PR31700 Processor
- Table of Contents
- List of Tables
- List of Figures
- 1 Introduction
- 2 Interfacing to the PR31500/PR31700
- 3 S1D13705 Host Bus Interface
- 4 Direct Connection to the Philips PR31500/PR31700
- 5 Using the ITE IT8368E PC Card Buffer
- 6 Software
- 7 Technical Support
- S5U13704/5 - TMPR3912/22U CPU Module
- Interfacing to the NEC VR4181A™ Microprocessor
- Interfacing to an 8-bit Processor