Document Outline

• S1D13705 TECHNICAL MANUAL
  • Customer Support Information
    • Comprehensive Support Tools
    • Evaluation / Demonstration Board
    • Chip Documentation
    • Software
    • Application Engineering Support
• Product Brief
  • FEATURES
  • System Block Diagram
  • DESCRIPTION
    • Memory Interface
    • CPU Interface
    • Display Support
    • Clock Source
    • Display Modes
    • Power Down Modes
    • Operating Voltage
    • Package
• Hardware Functional Specification
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
    • 1.1 Scope
    • 1.2 Overview Description
  • 2 Features
    • 2.1 Integrated Frame Buffer
    • 2.2 CPU Interface
    • 2.3 Display Support
    • 2.4 Display Modes
    • 2.5 Clock Source
    • 2.6 Miscellaneous
    • 2.7 Package
  • 3 Typical System Implementation Diagrams
    • Figure 31: Typical System Diagram (SH-4 Bus)
    • Figure 32: Typical System Diagram (SH-3 Bus)
    • Figure 33: Typical System Diagram (M68K #1 Bus)
    • Figure 34: Typical System Diagram (M68K #2 Bus)
    • Figure 35: Typical System Diagram (Generic #1 Bus)
    • Figure 36: Typical System Diagram (Generic #2 Bus - e.g. ISA Bus)
  • 4 Functional Block Diagram
    • Figure 41: System Block Diagram Showing Data Paths
    • 4.1 Functional Block Descriptions
      • 4.1.1 Host Interface
      • 4.1.2 Memory Controller
      • 4.1.3 Sequence Controller
      • 4.1.4 Look-Up Table
      • 4.1.5 LCD Interface
      • 4.1.6 Power Save
  • 5 Pins
    • 5.1 Pinout Diagram
      • Figure 51: Pinout Diagram
    • 5.2 Pin Description
      • Key:
      • 5.2.1 Host Interface
      • 5.2.2 LCD Interface
      • 5.2.3 Clock Input
      • 5.2.4 Miscellaneous
      • 5.2.5 Power Supply
    • 5.3 Summary of Configuration Options
      • Table 51: Summary of Power On/Reset Options
    • 5.4 Host Bus Interface Pin Mapping
      • Table 52: Host Bus Interface Pin Mapping
    • 5.5 LCD Interface Pin Mapping
      • Table 53: LCD Interface Pin Mapping
  • 6 D.C. Characteristics
    • Table 61: Absolute Maximum Ratings
    • Table 62: Recommended Operating Conditions for Core VDD = 3.3V ± 10%
    • Table 63: Input Specifications
    • Table 64: Output Specifications
  • 7 A.C. Characteristics
    • 7.1 Bus Interface Timing
      • 7.1.1 SH-4 Interface Timing
        • Figure 71: SH-4 Timing
        • Table 71: SH-4 Timing
      • 7.1.2 SH-3 Interface Timing
        • Figure 72: SH-3 Bus Timing
        • Table 72: SH-3 Bus Timing
      • 7.1.3 Motorola MC68K #1 Interface Timing
        • Figure 73: MC68K #1 Bus Timing (MC68000)
        • Table 73: MC68K #1 Bus Timing (MC68000)
      • 7.1.4 Motorola MC68K #2 Interface Timing
        • Figure 74: MC68K #2 Timing (MC68030)
        • Table 74: MC68K #2 Timing (MC68030)
      • 7.1.5 Generic #1 Interface Timing
        • Figure 75: Generic #1 Timing
        • Table 75: Generic #1 Timing
      • 7.1.6 Generic #2 Interface Timing
        • Figure 76: Generic #2 Timing
        • Table 76: Generic #2 Timing
    • 7.2 Clock Input Requirements
      • Figure 77: Clock Input Requirements for CLKI
      • Table 77: Clock Input Requirements for CLKI
      • Figure 78: Clock Input Requirements for BCLK
      • Table 78: Clock Input Requirements for BCLK
    • 7.3 Display Interface
      • 7.3.1 Power On/Reset Timing
        • Figure 79: LCD Panel Power On/Reset Timing
        • Table 79: LCD Panel Power On/Reset Timing
      • 7.3.2 Power Down/Up Timing
        • Figure 710: Power Down/Up Timing
        • Table 710: Power Down/Up Timing
      • 7.3.3 Single Monochrome 4-Bit Panel Timing
        • Figure 711: Single Monochrome 4-Bit Panel Timing
        • Figure 712: Single Monochrome 4-Bit Panel A.C. Timing
        • Table 711: Single Monochrome 4-Bit Panel A.C. Timing
      • 7.3.4 Single Monochrome 8-Bit Panel Timing
        • Figure 713: Single Monochrome 8-Bit Panel Timing
        • Figure 714: Single Monochrome 8-Bit Panel A.C. Timing
        • Table 712: Single Monochrome 8-Bit Panel A.C. Timing
      • 7.3.5 Single Color 4-Bit Panel Timing
        • Figure 715: Single Color 4-Bit Panel Timing
        • Figure 716: Single Color 4-Bit Panel A.C. Timing
        • Table 713: Single Color 4-Bit Panel A.C. Timing
      • 7.3.6 Single Color 8-Bit Panel Timing (Format 1)
        • Figure 717: Single Color 8-Bit Panel Timing (Format 1)
        • Figure 718: Single Color 8-Bit Panel A.C. Timing (Format 1)
        • Table 714: Single Color 8-Bit Panel A.C. Timing (Format 1)
      • 7.3.7 Single Color 8-Bit Panel Timing (Format 2)
        • Figure 719: Single Color 8-Bit Panel Timing (Format 2)
        • Figure 720: Single Color 8-Bit Panel A.C. Timing (Format 2)
        • Table 715: Single Color 8-Bit Panel A.C. Timing (Format 2)
      • 7.3.8 Dual Monochrome 8-Bit Panel Timing
        • Figure 721: Dual Monochrome 8-Bit Panel Timing
        • Figure 722: Dual Monochrome 8-Bit Panel A.C. Timing
        • Table 716: Dual Monochrome 8-Bit Panel A.C. Timing
      • 7.3.9 Dual Color 8-Bit Panel Timing
        • Figure 723: Dual Color 8-Bit Panel Timing
        • Figure 724: Dual Color 8-Bit Panel A.C. Timing
        • Table 717: Dual Color 8-Bit Panel A.C. Timing
      • 7.3.10 9/12-Bit TFT/D-TFD Panel Timing
        • Figure 725: 12-Bit TFT/D-TFD Panel Timing
        • Figure 726: TFT/D-TFD A.C. Timing
        • Table 718: TFT/D-TFD A.C. Timing
  • 8 Registers
    • 8.1 Register Mapping
    • 8.2 Register Descriptions
      • Table 81: Panel Data Format
      • Table 82: Gray Scale/Color Mode Selection
      • Table 83: High Performance Selection
      • Table 84: Inverse Video Mode Select Options
      • Table 85: Hardware Power Save/GPIO0 Operation
      • Table 86: Software Power Save Mode Selection
      • Figure 81: Screen-Register Relationship, Split Screen
      • Table 87: Selection of SwivelView Mode
      • Table 88: Selection of PCLK and MCLK in SwivelView Mode
  • 9 Frame Rate Calculation
  • 10 Display Data Formats
    • Figure 101: 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization
  • 11 Look-Up Table Architecture
    • 11.1 Monochrome Modes
      • 1 Bit-per-pixel Monochrome mode
        • Figure 111: 1 Bit-per-pixel Monochrome Mode Data Output Path
      • 2 Bit-per-pixel Monochrome Mode
        • Figure 112: 2 Bit-per-pixel Monochrome Mode Data Output Path
      • 4 Bit-per-pixel Monochrome Mode
        • Figure 113: 4 Bit-per-pixel Monochrome Mode Data Output Path
    • 11.2 Color Modes
      • 1 Bit-per-pixel Color Mode
        • Figure 114: 1 Bit-per-pixel Color Mode Data Output Path
      • 2 Bit-per-pixel Color Mode
        • Figure 115: 2 Bit-per-pixel Color Mode Data Output Path
      • 4 Bit-per-pixel Color Mode
        • Figure 116: 4 Bit-per-pixel Color Mode Data Output Path
      • 8 Bit-per-pixel Color Mode
        • Figure 117: 8 Bit-per-pixel Color Mode Data Output Path
  • 12 SwivelView™
    • 12.1 Default SwivelView Mode
      • Figure 121: Relationship Between The Screen Image and the Image Refreshed by S1D13705 in Default...
      • 12.1.1 How to Set Up Default SwivelView Mode
    • 12.2 Alternate SwivelView Mode
      • Figure 122: Relationship Between The Screen Image and the Image Refreshed by S1D13705 in Alterna...
      • 12.2.1 How to Set Up Alternate SwivelView Mode
    • 12.3 Comparison Between Default and Alternate SwivelView Modes
      • Table 121: Default and Alternate SwivelView Mode Comparison
    • 12.4 SwivelView Mode Limitations
  • 13 Power Save Modes
    • Table 131: Power Save Mode Selection
    • 13.1 Software Power Save Mode
      • Table 132: Software Power Save Mode Summary
    • 13.2 Hardware Power Save Mode
      • Table 133: Hardware Power Save Mode Summary
    • 13.3 Power Save Mode Function Summary
      • Table 134: Power Save Mode Function Summary
    • 13.4 Panel Power Up/Down Sequence
      • Figure 131: Panel On/Off Sequence
    • 13.5 Turning Off BCLK Between Accesses
    • 13.6 Clock Requirements
      • Table 135: S1D13705 Internal Clock Requirements
  • 14 Mechanical Data
    • Figure 141: Mechanical Drawing QFP14
  • 15 Sales and Technical Support
• Programming Notes and Examples
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Initialization
    • 2.1 Display Buffer Location
    • 2.2 Register Values
      • Table 21: S1D13705 Initialization Sequence
    • 2.3 Frame Rate Calculation
  • 3 Memory Models
    • 3.1 1 Bit-Per-Pixel (2 Colors/Gray Shades)
      • Figure 31: Pixel Storage for 1 Bpp (2 Colors/Gray Shades) in One Byte of Display Buffer
    • 3.2 2 Bit-Per-Pixel (4 Colors/Gray Shades)
      • Figure 32: Pixel Storage for 2 Bpp (4 Colors/Gray Shades) in One Byte of Display Buffer
    • 3.3 4 Bit-Per-Pixel (16 Colors/Gray Shades)
      • Figure 33: Pixel Storage for 4 Bpp (16 Colors/Gray Shades) in One Byte of Display Buffer
    • 3.4 Eight Bit-Per-Pixel (256 Colors)
      • Figure 34: Pixel Storage for 8 Bpp (256 Colors) in One Byte of Display Buffer
  • 4 Look-Up Table (LUT)
    • 4.1 Look-Up Table Registers
    • 4.2 Look-Up Table Organization
      • 4.2.1 Color Modes
        • Table 41: Recommended LUT Values for 1 Bpp Color Mode
        • Table 42: Example LUT Values for 2 Bpp Color Mode
        • Table 43: Suggested LUT Values to Simulate VGA Default 16 Color Palette
        • Table 44: Suggested LUT Values to Simulate VGA Default 256 Color Palette
      • 4.2.2 Gray Shade Modes
        • Table 45: Recommended LUT Values for 1 Bpp Gray Shade
        • Table 46: Suggested Values for 2 Bpp Gray Shade
        • Table 47: Suggested LUT Values for 4 Bpp Gray Shade
  • 5 Advanced Techniques
    • 5.1 Virtual Display
      • Figure 51: Viewport Inside a Virtual Display
      • 5.1.1 Registers
      • 5.1.2 Examples
    • 5.2 Panning and Scrolling
      • 5.2.1 Registers
        • Table 51: Number of Pixels Panned Using Start Address
      • 5.2.2 Examples
    • 5.3 Split Screen
      • Figure 52: 320x240 Single Panel For Split Screen
      • 5.3.1 Registers
      • 5.3.2 Examples
  • 6 LCD Power Sequencing and Power Save Modes
    • 6.1 LCD Power Sequencing
    • 6.2 Registers
    • 6.3 LCD Enable/Disable
  • 7 Hardware Rotation
    • 7.1 Introduction To Hardware Rotation
    • 7.2 Default Portrait Mode
      • Figure 71: Relationship Between the Default Mode Screen Image and the Image Refreshed by S1D13705
    • 7.3 Alternate Portrait Mode
      • Figure 72: Relationship Between the Alternate Mode Screen Image and the Image Refreshed by S1D13705
    • 7.4 Registers
    • 7.5 Limitations
      • Table 71: Default and Alternate Portrait Mode Comparison
    • 7.6 Examples
  • 8 Identifying the S1D13705
  • 9 Hardware Abstraction Layer (HAL)
    • 9.1 Introduction
    • 9.2 Contents of the HAL_STRUCT
    • 9.3 Using the HAL library
    • 9.4 API for 13705HAL
      • Table 91: HAL Functions
      • 9.4.1 Initialization
      • 9.4.2 General HAL Support
      • 9.4.3 Advanced HAL Functions
      • 9.4.4 Register / Memory Access
      • 9.4.5 Power Save
      • 9.4.6 Drawing
      • 9.4.7 LUT Manipulation
    • 9.5 Porting LIBSE to a new target platform
      • 9.5.1 Building the LIBSE library for SH3 target example
      • 9.5.2 Building the HAL library for the target example
  • 10 Sample Code
    • 10.1 Sample code using the S1D13705 HAL API
    • 10.2 Sample code without using the S1D13705 HAL API
    • 10.3 Header Files
• Register Summary
• 13705CFG Configuration Program
  • Table of Contents
  • 13705CFG
    • S1D13705 Supported Evaluation Platforms
    • Installation
    • Usage
    • 13705CFG Configuration Tabs
      • General Tab
      • Preferences Tab
      • Clocks Tab
      • Panel Tab
      • Panel Power Tab
      • Registers Tab
    • 13705CFG Menus
      • Open...
      • Save
      • Save As...
      • Configure Multiple
      • Export
      • Enable Tooltips
      • ERD on the Web
      • About 13705CFG
    • Comments
• 13705SHOW Demonstration Program
  • 13705SHOW
    • S1D13705 Supported Evaluation Platforms
    • Installation
    • Usage
    • Comments
    • Program Messages
• 13705SPLT Display Utility
  • 13705SPLT
    • S1D13705 Supported Evaluation Platforms
    • Installation
    • Usage
    • 13705SPLT Example
    • Program Messages
• 13705VIRT Display Utility
  • 13705VIRT
    • S1D13705 Supported Evaluation Platforms
    • Installation
    • Usage
    • 13705VIRT Example
    • Program Messages
• 13705PLAY Diagnostic Utility
  • 13705PLAY
    • S1D13705 Supported Evaluation Platforms
    • Installation
    • Usage
    • 13705PLAY Example
    • Scripting
    • Comments
    • Program Messages
• 13705BMP Demonstration Program
  • 13705BMP
    • Installation
    • Usage
    • Comments
    • Program Messages
• 13705PWR Power Save Utility
  • 13705PWR
    • S1D13705 Supported Evaluation Platforms
    • Installation
    • Usage
    • Program Messages
• Windows® CE 2.x Display Drivers
  • WINDOWS® CE 2.x DISPLAY DRIVERS
    • Example Driver Builds
    • Installation for CEPC Environment
    • Configuration
      • Compile Switches
      • Mode File
    • Comments
• Wind River WindML v2.0 Display Drivers
  • Wind River WindML v2.0 DISPLAY DRIVERS
    • Building a WindML v2.0 Display Driver
      • 1. Create a working directory and unzip the WindML display driver into it.
      • 2. Configure for the target execution model.
      • 3. Build a boot ROM image.
      • 4. Create a bootable disk (in drive A:).
      • 5. If necessary, generate a new mode0.h configuration file.
      • 6. Build the WindML v2.0 library.
      • 7. Open the S1D13705 workspace.
      • 8. Add support for single line comments.
        • a. In the Tornado “Workspace Views” window, click on the “Builds” tab.
        • b. Expand the “8bpp Builds” view by clicking on the “+” next to it. The expanded view will contai...
        • c. Select the “C/C++ compiler” tab to display the command switches used in the build. Remove the ...
      • 9. Compile the VxWorks image.
      • 10. Copy the VxWorks file to the diskette.
      • 11. Start the VxWorks demo.
• Wind River UGL v1.2 Display Drivers
  • Wind River UGL v1.2 Display Drivers
    • Building a UGL v1.2 Display Driver
      • 1. Create a working directory and unzip the UGL display driver into it.
      • 2. Configure for the target execution model.
      • 3. Build a boot ROM image.
      • 4. Create a bootable disk (in drive A:).
      • 5. If necessary, generate a new mode0.h configuration file.
      • 6. Open the S1D13705 workspace.
      • 7. Add support for single line comments.
        • a. In the Tornado “Workspace” window, click on the “Builds” tab.
        • b. Expand the “8bpp Builds” view by clicking on the “+” next to it. The expanded view will contai...
        • c. Select the “C/C++ compiler” tab to display the command switches used in the build. Remove the ...
      • 8. Compile the VxWorks image.
      • 9. Copy the VxWorks file to the diskette.
      • 10. Start the VxWorks demo.
• Linux Console Driver
  • Linux Console Driver
    • Building the Console Driver for Linux Kernel 2.2.x
      • 1. Acquire the Linux kernel source code.
      • 2. Unzip the console driver files.
      • 3. Copy the console driver files to the build directory.
      • 4. Modify s1d13705.h
      • 5. Configure the video options.
      • 6. Compile and install the kernel
      • 7. Boot to the Linux operating system
    • Building the Console Driver for Linux Kernel 2.4.x
      • 1. Acquire the Linux kernel source code.
      • 2. Unzip the console driver files.
      • 3. Copy the console driver files to the build directory. Make the directory /usr/src/linux/driver...
      • 4. Modify s1d13705.h
      • 5. Configure the video options.
      • 6. Compile and install the kernel
      • 7. Boot to the Linux operating system
• QNX Photon v2.0 Display Driver
  • QNX Photon v2.0 Display Driver
    • Building the Photon v2.0 Display Driver
      • Unpack the Graphics Driver Development Kit Archive
      • Configure the Driver
      • Build the Driver
      • Installing the Driver
      • Run the Driver
    • Comments
• S1D13XXX 32-Bit Windows Device Driver Installation Guide
  • S1D13XXX 32-Bit Windows Device Driver Installation Guide
    • Driver Requirements
    • Installation
      • Windows NT Version 4.0
      • Windows 2000
      • Windows 98/ME
      • Windows 95 OSR2
      • Previous Versions of Windows 95
• S5U13705B00C Rev. 1.0 ISA Bus Evaluation Board User Manual
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
    • 1.1 Features
  • 2 Installation and Configuration
    • Table 21: Configuration DIP Switch Settings
    • Table 22: Host Bus Selection
    • Table 23: Jumper Settings
  • 3 LCD Interface Pin Mapping
    • Table 31: LCD Signal Connector (J5) Pinout
  • 4 CPU/Bus Interface Connector Pinouts
    • Table 41: CPU/BUS Connector (H1) Pinout
    • Table 42: CPU/BUS Connector (H2) Pinout
  • 5 Host Bus Interface Pin Mapping
    • Table 51: Host Bus Interface Pin Mapping
  • 6 Technical Description
    • 6.1 Embedded Memory Support
    • 6.2 ISA Bus Support
      • 6.2.1 Display Adapter Card Support
      • 6.2.2 Expanded Memory Manager Support
    • 6.3 Non-ISA Bus Support
    • 6.4 Decoding Logic
    • 6.5 Clock Input Support
    • 6.6 LCD Panel Voltage Setting
    • 6.7 Monochrome LCD Panel Support
    • 6.8 Color Passive LCD Panel Support
    • 6.9 Color TFT/D-TFD LCD Panel Support
    • 6.10 Power Save Modes
    • 6.11 Adjustable LCD Panel Negative Power Supply
    • 6.12 Adjustable LCD Panel Positive Power Supply
    • 6.13 CPU/Bus Interface Header Strips
  • 7 Parts List
  • 8 Schematic Diagrams
    • Figure 81: S1D13705B00C Schematic Diagram (1 of 4)
    • Figure 82: S1D13705B00C Schematic Diagram (2 of 4)
    • Figure 83: S1D13705B00C Schematic Diagram (3 of 4)
    • Figure 84: S1D13705B00C Schematic Diagram (4 of 4)
• S5U13705B00C Rev. 2.0 Evaluation Board User Manual
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Features
  • 3 Installation and Configuration
    • 3.1 Configuration DIP Switches
      • Figure 31: Configuration DIP Switch (SW1) Location
      • Table 31: Configuration DIP Switch Settings
    • 3.2 Configuration Jumpers
      • Table 32: Jumper Summary
      • Figure 32: Configuration Jumper (JP1) Location
      • Figure 33: Configuration Jumper (JP2) Location
      • Figure 34: Configuration Jumper (JP3) Location
      • Figure 35: Configuration Jumper (JP4) Location
      • Figure 36: Configuration Jumper (JP5) Location
      • Figure 37: Configuration Jumper (JP6) Location
      • Figure 38: Configuration Jumper (JP7) Location
  • 4 CPU Interface
    • 4.1 CPU Interface Pin Mapping
      • Table 41: CPU Interface Pin Mapping
    • 4.2 CPU Bus Connector Pin Mapping
      • Table 42: CPU Bus Connector (H1) Pinout
      • Table 43: CPU Bus Connector (H2) Pinout
  • 5 LCD Interface Pin Mapping
    • Table 51: LCD Signal Connector (J5)
  • 6 Technical Description
    • 6.1 PCI Bus Support
    • 6.2 Direct Host Bus Interface Support
    • 6.3 S1D13705 Embedded Memory
    • 6.4 Adjustable LCD Panel Positive Power Supply (VDDH)
    • 6.5 Adjustable LCD Panel Negative Power Supply (VLCD)
    • 6.6 Passive/Active LCD Panel Support
    • 6.7 Power Save Modes
    • 6.8 Clock Options
  • 7 Software
  • 8 References
    • 8.1 Documents
    • 8.2 Document Sources
  • 9 Parts List
  • 10 Schematics
    • Figure 101: S1D13705B00C Schematics (1 of 5)
    • Figure 102: S1D13705B00C Schematics (2 of 5)
    • Figure 103: S1D13705B00C Schematics (3 of 5)
    • Figure 104: S1D13705B00C Schematics (4 of 5)
    • Figure 105: S1D13705B00C Schematics (5 of 5)
  • 11 Board Layout
  • 12 Technical Support
    • 12.1 EPSON LCD Controllers (S1D13705)
• Windows® CE 3.x Display Drivers
  • WINDOWS® CE 3.x DISPLAY DRIVERS
    • Example Driver Builds
    • Installation for CEPC Environment
    • Configuration
      • Compile Switches
      • Mode File
      • Resource Management Issues
    • Comments
• Interfacing to the Toshiba MIPS TMPR3912 Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the TMPR3912
  • 3 S1D13705 Host Bus Interface
    • 3.1 Host Bus Pin Connection
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Generic #1 Interface Mode
    • 3.3 Generic #2 Interface Mode
  • 4 Direct Connection to the Toshiba TMPR3912
    • 4.1 General Description
      • Figure 41: S1D13705 to TMPR3912 Direct Connection
    • 4.2 Memory Mapping and Aliasing
    • 4.3 S1D13705 Configuration
      • Table 41: S1D13705 Configuration for Direct Connection
  • 5 Using the ITE IT8368E PC Card Buffer
    • 5.1 Hardware Description
      • Figure 51: S1D13705 to TMPR3912 Connection Using an IT8368E
    • 5.2 IT8368E Configuration
    • 5.3 Memory Mapping and Aliasing
      • Table 51: TMPR3912 to PC Card Slots Address Mapping With and Without the IT8368E
    • 5.4 S1D13705 Configuration
      • Table 52: S1D13705 Configuration Using the IT8368E
  • 6 Software
  • 7 Technical Support
    • 7.1 EPSON LCD Controllers (S1D13705)
    • 7.2 Toshiba MIPS TMPR3912 Processor
    • 7.3 ITE IT8368E
• S1D13705 Power Consumption
  • 1 S1D13705 Power Consumption
    • 1.1 Conditions
      • Table 11: S1D13705 Total Power Consumption
  • 2 Summary
• Interfacing to the Motorola ‘Dragonball’ Family of Microprocessors
  • Document Number: X27A-G-007-04
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the MC68328
    • 2.1 The MC68328 System Bus
    • 2.2 Chip-Select Module
    • 2.3 S1D13705 Host Bus Interface
      • 2.3.1 Host Bus Pin Connection
        • Table 21: Host Bus Interface Pin Mapping
      • 2.3.2 Generic #1 Interface Mode
      • 2.3.3 MC68K #1 Interface Mode
    • 2.4 MC68328 To S1D13705 Interface
      • 2.4.1 Hardware Description
        • Using The MC68K #1 Host Bus Interface
          • Figure 21: Typical Implementation of MC68328 to S1D13705 Interface - MC68K #1
        • Using The Generic #1 Host Bus Interface
          • Figure 22: Typical Implementation of MC68328 to S1D13705 Interface - Generic #1
      • 2.4.2 S1D13705 Hardware Configuration
        • Table 22: Summary of Power-On/Reset Options
        • Table 23: Host Bus Interface Selection
      • 2.4.3 MC68328 Chip Select Configuration
  • 3 Interfacing to the MC68EZ328
    • 3.1 The MC68EZ328 System Bus
    • 3.2 Chip-Select Module
    • 3.3 S1D13705 Host Bus Interface
      • 3.3.1 Host Bus Pin Connection
        • Table 31: Host Bus Interface Pin Mapping
      • 3.3.2 Generic #1 Interface Mode
    • 3.4 MC683EZ28 To S1D13705 Interface
      • 3.4.1 Hardware Description
        • Figure 31: Typical Implementation of MC68EZ328 to S1D13705 Interface - Generic #1
      • 3.4.2 S1D13705 Hardware Configuration
        • Table 32: Summary of Power-On/Reset Options
        • Table 33: Host Bus Interface Selection
      • 3.4.3 MC68EZ328 Chip Select Configuration
  • 4 Interfacing to the MC68VZ328
    • 4.1 The MC68VZ328 System Bus
    • 4.2 Chip-Select Module
    • 4.3 S1D13705 Host Bus Interface
      • 4.3.1 Host Bus Pin Connection
        • Table 41: Host Bus Interface Pin Mapping
      • 4.3.2 Generic #1 Interface Mode
      • 4.3.3 MC68K #1 Interface Mode
    • 4.4 MC68VZ328 To S1D13705 Interface
      • 4.4.1 Hardware Description
        • Using The MC68K #1 Host Bus Interface
          • Figure 41: Typical Implementation of MC68VZ328 to S1D13705 Interface - MC68K #1
        • Using The Generic #1 Host Bus Interface
          • Figure 42: Typical Implementation of MC68VZ328 to S1D13705 Interface - Generic #1
      • 4.4.2 S1D13705 Hardware Configuration
        • Table 42: Summary of Power-On/Reset Options
        • Table 43: Host Bus Interface Selection
      • 4.4.3 MC68VZ328 Chip Select and Pin Configuration
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD Controllers (S1D13705)
    • 7.2 Motorola Dragonball Processors
• Interfacing to the NEC VR4102/VR4111 Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the NEC VR4102/VR4111
    • 2.1 The NEC VR4102/VR4111 System Bus
      • 2.1.1 Overview
      • 2.1.2 LCD Memory Access Cycles
        • Figure 21: NEC VR4102/VR4111 Read/Write Cycles
  • 3 S1D13705 Host Bus Interface
    • 3.1 Host Bus Pin Connection
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Generic #2 Interface Mode
  • 4 VR4102/VR4111 to S1D13705 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of VR4102/VR4111 to S1D13705 Interface
    • 4.2 S1D13705 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
      • Table 42: Host Bus Selection
    • 4.3 NEC VR4102/VR4111 Configuration
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD Controllers (S1D13705)
    • 7.2 NEC Electronics Inc.
• Interfacing to the PC Card Bus
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the PC Card Bus
    • 2.1 The PC Card System Bus
      • 2.1.1 PC Card Overview
      • 2.1.2 Memory Access Cycles
        • Figure 21: PC Card Read Cycle
        • Figure 22: PC Card Write Cycle
  • 3 S1D13705 Bus Interface
    • 3.1 Host Bus Pin Connection
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Generic #2 Interface Mode
  • 4 PC Card to S1D13705 Interface
    • 4.1 Hardware Connections
      • Figure 41: Typical Implementation of PC Card to S1D13705 Interface
    • 4.2 S1D13705 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
      • Table 42: Host Bus Interface Selection
    • 4.3 Register/Memory Mapping
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD Controllers (S1D13705)
    • 7.2 PC Card Standard
• Interfacing to the Motorola MPC821 Microprocessor
  • Document Number: X27A-G-010-02
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the MPC821
    • 2.1 The MPC8xx System Bus
    • 2.2 MPC821 Bus Overview
      • 2.2.1 Normal (Non-Burst) Bus Transactions
        • Figure 21: Power PC Memory Read Cycle
        • Figure 22: Power PC Memory Write Cycle
      • 2.2.2 Burst Cycles
    • 2.3 Memory Controller Module
      • 2.3.1 General-Purpose Chip Select Module (GPCM)
      • 2.3.2 User-Programmable Machine (UPM)
  • 3 S1D13705 Host Bus Interface
    • 3.1 Host Bus Interface Modes
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Generic #1 Host Bus Interface Mode
  • 4 MPC821 to S1D13705 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of MPC821 to S1D13705 Interface
    • 4.2 MPC821ADS Evaluation Board Hardware Connections
      • Table 41: List of Connections from MPC821ADS to S1D13705 
    • 4.3 S1D13705 Hardware Configuration
      • Table 42: Configuration Settings
      • Table 43: Host Bus Selection
    • 4.4 MPC821 Chip Select Configuration
    • 4.5 Test Software
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD/CRT Controllers (S1D13705)
    • 7.2 Motorola MPC821 Processor
• Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
  • Document Number: X27A-G-011-02
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the MCF5307
    • 2.1 The MCF5307 System Bus
      • 2.1.1 Overview
      • 2.1.2 Normal (Non-Burst) Bus Transactions
        • Figure 21: MCF5307 Memory Read Cycle
        • Figure 22: MCF5307 Memory Write Cycle
      • 2.1.3 Burst Cycles
    • 2.2 Chip-Select Module
  • 3 S1D13705 Bus Interface
    • 3.1 Host Bus Pin Connection
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Generic #1 Interface Mode
  • 4 MCF5307 To S1D13705 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of MCF5307 to S1D13705 Interface
    • 4.2 S1D13705 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
      • Table 42: Host Bus Interface Selection
    • 4.3 MCF5307 Chip Select Configuration
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 EPSON LCD Controllers (S1D13705)
    • 7.2 Motorola MCF5307 Processor
• Interfacing to the Philips MIPS PR31500/PR31700 Processor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the PR31500/PR31700
  • 3 S1D13705 Host Bus Interface
    • 3.1 Host Bus Pin Connection
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Generic #1 Interface Mode
    • 3.3 Generic #2 Interface Mode
  • 4 Direct Connection to the Philips PR31500/PR31700
    • 4.1 General Description
      • Figure 41: S1D13705 to PR31500/PR31700 Direct Connection
    • 4.2 Memory Mapping and Aliasing
    • 4.3 S1D13705 Configuration and Pin Mapping
      • Table 41: S1D13705 Configuration for Direct Connection
  • 5 Using the ITE IT8368E PC Card Buffer
    • 5.1 Hardware Description
      • Figure 51: S1D13705 to PR31500/PR31700 Connection Using an IT8368E
    • 5.2 IT8368E Configuration
    • 5.3 Memory Mapping and Aliasing
      • Table 51: PR31500/PR31700 to PC Card Slots Address Mapping With and Without the IT8368E
    • 5.4 S1D13705 Configuration
      • Table 52: S1D13705 Configuration Using the IT8368E
  • 6 Software
  • 7 Technical Support
    • 7.1 EPSON LCD Controllers (S1D13705)
    • 7.2 Philips MIPS PR31500/PR31700 Processor
    • 7.3 ITE IT8368E
• S5U13704/5 - TMPR3912/22U CPU Module
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
    • 1.1 General Description
  • 2 S1D13704/5 Bus Interface
    • 2.1 Bus Interface Modes
    • 2.2 Generic #2 Interface Mode
  • 3 TMPR3912/22U and S1D13704/5 Interface
    • 3.1 Hardware Connections
      • Figure 31: S1D13704 to TMPR3912/22U Interface
    • 3.2 Memory Mapping and Aliasing
    • 3.3 S1D13704/5 Configuration and Pin Mapping
      • Table 31: S1D13704/5 Configuration for Generic #2 Bus Interface
      • Table 32: S1D13704/5 Generic #2 Interface Pin Mapping
  • 4 CPU Module Description
    • 4.1 Clock Signals
      • 4.1.1 BUSCLK
      • 4.1.2 CLKI
    • 4.2 LCD Connectors
      • 4.2.1 50-pin LCD Module Connector, J3
      • 4.2.2 Standard Epson LCD Connector, J4
    • 4.3 LCD Controller
      • 4.3.1 S1D13704 vs. S1D13705
      • 4.3.2 LCDPWR Polarity
      • 4.3.3 S1D13704\75 Chip Select
• Interfacing to the NEC VR4181A™ Microprocessor
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to the NEC VR4181A
    • 2.1 The NEC VR4181A System Bus
      • 2.1.1 Overview
      • 2.1.2 LCD Memory Access Signals
  • 3 S1D13705 Host Bus Interface
    • 3.1 Host Bus Pin Connection
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Generic #2 Interface Mode
  • 4 VR4181A to S1D13705 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of VR4181A to S1D13705 Interface
    • 4.2 S1D13705 Hardware Configuration
      • Table 41: Summary of Power-On/Reset Options
      • Table 42: Host Bus Selection
    • 4.3 NEC VR4181A Configuration
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD Controllers (S1D13705)
    • 7.2 NEC Electronics Inc.
• Interfacing to an 8-bit Processor
  • Document Number: X27A-G-015-01
  • Table of Contents
  • List of Tables
  • List of Figures
  • 1 Introduction
  • 2 Interfacing to an 8-bit Processor
    • 2.1 The Generic 8-bit Processor System Bus
  • 3 S1D13705 Bus Interface
    • 3.1 Host Bus Pin Connection
      • Table 31: Host Bus Interface Pin Mapping
    • 3.2 Generic #2 Interface Mode
  • 4 8-Bit Processor to S1D13705 Interface
    • 4.1 Hardware Description
      • Figure 41: Typical Implementation of an 8-bit Processor to the S1D13705 Generic #2 Interface
    • 4.2 S1D13705 Hardware Configuration
      • Table 41: Configuration Settings
      • Table 42: Host Bus Selection
    • 4.3 Register/Memory Mapping
  • 5 Software
  • 6 References
    • 6.1 Documents
    • 6.2 Document Sources
  • 7 Technical Support
    • 7.1 Epson LCD/CRT Controllers (S1D13705)