Dual serial controller, Field programmable gate array, Baseboard management controller – HP AD117-9003A-ED3 User Manual

Page 26

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— Two general purpose 32-bit registers
— Semaphore registers
— Monarch selection registers
— Test and Reset register

•

Reset and INIT generation

Dual Serial Controller

The dual serial controller is a dual universal asynchronous receiver and transmitter (DUART).
This chip provides enhanced UART functions with 16-byte first-in, first-out (FIFO), a modem
control interface. Registers on this chip provide onboard error indications and operation status.
An internal loopback capability provides onboard diagnostics.

Features include:

•

Data rates up to 115.2 kbps

•

16550A fully compatible controller

•

A 16-byte transmit FIFO that reduces the bandwidth requirement of the external CPU

•

A 16-byte receive FIFO with four selectable interrupt trigger levels and error flags that reduce
the bandwidth requirement of the external CPU

•

UART control that provides independent transmit and receive

•

Modem control signals (-CTS, -RTS, -DSR, -DTR, -RI, -CD, and software controllable line
break)

•

Programmable character lengths (5, 6, 7, 8) with Even, Odd or No Parity

•

A status report register

Field Programmable Gate Array

The field programmable gate array (FPGA) provides ACPI and LPC support for the PDH bus
and provides these features:

•

ACPI 2.0 interface

•

LPC bus interface to support BMC

•

Decoding logic for PDH devices

Baseboard Management Controller

The baseboard management controller (BMC) supports the industry-standard Intelligent Platform
Management Interface (IPMI) specification. This specification describes the management features
that have been built into the system board. These features include: local and remote diagnostics,
console support, configuration management, hardware management, and troubleshooting.

The baseboard management controller provides the following:

•

Compliance with IPMI 1.0

•

Tachometer inputs for fan speed monitoring

•

Pulse width modulator outputs for fan speed control

•

Push-button inputs for front panel buttons and switches

•

One serial port, multiplexed with the server console port

•

Remote access and intelligent chassis management bus (ICMB) support

•

Three I2C primary/secondary ports (one port is used for IPMB)

•

Low pin count (LPC) bus provides access to three keyboard controller style (KCS) and
one-block transfer (BT) interface

•

32-bit ARM7 processor

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Introduction

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