Document Outline

• CHAPTER 1 OVERVIEW
  • 1.1 Features of MB89202/F202RA Series
  • 1.2 MB89202/F202RA Series Product Lineup
  • 1.3 Differences between Models
  • 1.4 Block Diagram of MB89202/F202RA Series
  • 1.5 Pin Assignment
  • 1.6 Package Dimensions
  • 1.7 Pin Functions Description
  • 1.8 I/O Circuit Types
• CHAPTER 2 HANDLING DEVICES
  • 2.1 Precautions on Handling Devices
• CHAPTER 3 CPU
  • 3.1 Memory Space
    • 3.1.1 Specific-purpose Areas
    • 3.1.2 Location of 16-bit Data on Memory
  • 3.2 Dedicated Register
    • 3.2.1 Condition Code Register (CCR)
    • 3.2.2 Register Bank Pointer (RP)
  • 3.3 General-Purpose Registers
  • 3.4 Interrupts
    • 3.4.1 Interrupt Level Setting Registers (ILR1 to ILR4)
    • 3.4.2 Steps in the Interrupt Operation
    • 3.4.3 Multiple Interrupts
    • 3.4.4 Interrupt Processing Time
    • 3.4.5 Stack Operation at Interrupt Processing
    • 3.4.6 Stack Area for Interrupt Processing
  • 3.5 Reset
    • 3.5.1 Reset Flag Register (RSFR)
    • 3.5.2 External Reset Pin
    • 3.5.3 Reset Operation
    • 3.5.4 State of Each Pin at Reset
  • 3.6 Clock
    • 3.6.1 Clock Generator
    • 3.6.2 Clock Controller
    • 3.6.3 System Clock Control Register (SYCC)
    • 3.6.4 Clock Mode
    • 3.6.5 Oscillation Stabilization Wait Time
  • 3.7 Standby Mode (Low-Power Consumption Mode)
    • 3.7.1 Operations in Standby Mode
    • 3.7.2 Sleep Mode
    • 3.7.3 Stop Mode
    • 3.7.4 Standby Control Register (STBC)
    • 3.7.5 Diagram for State Transition in Standby Mode
    • 3.7.6 Notes on Standby Mode
  • 3.8 Memory Access Mode
• CHAPTER 4 I/O PORTS
  • 4.1 Overview of I/O Ports
  • 4.2 Port 0
    • 4.2.1 Registers of Port 0 (PDR0, DDR0, and PUL0)
    • 4.2.2 Operations of Port 0 Functions
  • 4.3 Port 3
    • 4.3.1 Registers of Port 3 (PDR3, DDR3, PUL3)
    • 4.3.2 Operations of Port 3 Functions
  • 4.4 Port 4
    • 4.4.1 Registers of Port 4 (PDR4)
    • 4.4.2 Operations of Port 4 Functions
  • 4.5 Port 5
    • 4.5.1 Registers of Port 5 (PDR5, DDR5, PUL5)
    • 4.5.2 Operations of Port 5 Functions
  • 4.6 Port 6
    • 4.6.1 Registers of Port 6 (PDR6, DDR6, PUL6)
    • 4.6.2 Operations of Port 6 Functions
  • 4.7 Port 7
    • 4.7.1 Registers of Port 7 (PDR7, DDR7, PUL7)
    • 4.7.2 Operations of Port 7 Functions
  • 4.8 Programming Example of I/O Port
• CHAPTER 5 TIME-BASE TIMER
  • 5.1 Overview of Time-base Timer
  • 5.2 Configuration of Time-base Timer
  • 5.3 Time-base Timer Control Register (TBTC)
  • 5.4 Interrupt of Time-base Timer
  • 5.5 Operations of Time-base Timer Functions
  • 5.6 Notes on Using Time-base Timer
  • 5.7 Program Example for Time-base Timer
• CHAPTER 6 WATCHDOG TIMER
  • 6.1 Overview of Watchdog Timer
  • 6.2 Configuration of Watchdog Timer
  • 6.3 Watchdog Control Register (WDTC)
  • 6.4 Operations of Watchdog Timer Functions
  • 6.5 Notes on Using Watchdog Timer
  • 6.6 Program Example for Watchdog Timer
• CHAPTER 7 8-BIT PWM TIMER
  • 7.1 Overview of 8-bit PWM Timer
  • 7.2 Configuration of 8-bit PWM Timer
  • 7.3 Pin of 8-bit PWM Timer
  • 7.4 Registers of 8-bit PWM Timer
    • 7.4.1 PWM Control Register (CNTR)
    • 7.4.2 PWM Compare Register (COMR)
  • 7.5 Interrupt of 8-bit PWM Timer
  • 7.6 Operations of the Interval Timer Functions
  • 7.7 Operations of the 8-bit PWM Timer Functions
  • 7.8 States in Each Mode During Operation
  • 7.9 Notes on Using 8-bit PWM Timer
  • 7.10 Program Example for PWM Timer
• CHAPTER 8 8/16-BIT CAPTURE TIMER/ COUNTER
  • 8.1 Overview of 8/16-bit Capture Timer/Counter
  • 8.2 Configuration of 8/16-bit Capture Timer/Counter
  • 8.3 Pins of 8/16-bit Capture Timer/Counter
  • 8.4 Registers of 8/16-bit Capture Timer/Counter
    • 8.4.1 Capture Control Register (TCCR)
    • 8.4.2 Timer 0 Control Register (TCR0)
    • 8.4.3 Timer 1 Control Register (TCR1)
    • 8.4.4 Timer Output Control Register (TCR2)
    • 8.4.5 Timer 0 Data Register (TDR0)
    • 8.4.6 Timer 1 Data Register (TDR1)
    • 8.4.7 Capture Data Registers H and L (TCPH and TCPL)
  • 8.5 8/16-bit Capture Timer/Counter of Interrupts
  • 8.6 Explanation of Operations of Interval Timer Functions
  • 8.7 Operation of Counter Functions
  • 8.8 Functions of Operations of Capture Functions
  • 8.9 8/16-bit Capture Timer/Counter Operation in Each Mode
  • 8.10 Notes on Using 8/16-bit Capture Timer/Counter
  • 8.11 Program Example for 8/16-bit Capture Timer/Counter
• CHAPTER 9 12-BIT PPG TIMER
  • 9.1 Overview of 12-bit PPG Timer
  • 9.2 Configuration of 12-bit PPG Timer Circuit
  • 9.3 Pin of 12-bit PPG Timer
  • 9.4 Registers of 12-bit PPG Timer
    • 9.4.1 12-bit PPG Control Register 1 (RCR21)
    • 9.4.2 12-bit PPG Control Register 2 (RCR22)
    • 9.4.3 12-bit PPG Control Register 3 (RCR23)
    • 9.4.4 12-bit PPG Control Register 4 (RCR24)
  • 9.5 Operations of 12-bit PPG Timer Functions
  • 9.6 Notes on Using 12-bit PPG Timer
  • 9.7 Program Example for 12-bit PPG Timer
• CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
  • 10.1 Overview of External Interrupt Circuit 1
  • 10.2 Configuration of External Interrupt Circuit 1
  • 10.3 Pins of External Interrupt Circuit 1
  • 10.4 Registers of External Interrupt Circuit 1
    • 10.4.1 External Interrupt Control Register 1 (EIC1)
    • 10.4.2 External Interrupt Control Register 2 (EIC2)
  • 10.5 Interrupt of External Interrupt Circuit 1
  • 10.6 Operations of External Interrupt Circuit 1
  • 10.7 Program Example for External Interrupt Circuit 1
• CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
  • 11.1 Overview of External Interrupt Circuit 2
  • 11.2 Configuration of External Interrupt Circuit 2
  • 11.3 Pins of External Interrupt Circuit 2
  • 11.4 Registers of External Interrupt Circuit 2
    • 11.4.1 External Interrupt 2 Control Register (EIE2)
    • 11.4.2 External Interrupt 2 Flag Register (EIF2)
  • 11.5 Interrupt of External Interrupt Circuit 2
  • 11.6 Operations of External Interrupt Circuit 2
  • 11.7 Program Example for External Interrupt Circuit 2
• CHAPTER 12 A/D CONVERTER
  • 12.1 Overview of A/D Converter
  • 12.2 Configuration of A/D Converter
  • 12.3 Pins of A/D Converter
  • 12.4 Registers of A/D Converter
    • 12.4.1 A/D Control Register 1 (ADC1)
    • 12.4.2 A/D Control Register 2 (ADC2)
    • 12.4.3 A/D Data Register (ADDH and ADDL)
    • 12.4.4 A/D Enable Register (ADEN)
  • 12.5 Interrupt of A/D Converter
  • 12.6 Operations of A/D Converter Functions
  • 12.7 Notes on Using A/D Converter
  • 12.8 Program Example for A/D Converter
• CHAPTER 13 UART
  • 13.1 Overview of UART
  • 13.2 Configuration of UART
  • 13.3 Pins of UART
  • 13.4 Registers of UART
    • 13.4.1 Serial Mode Control Register (SMC)
    • 13.4.2 Serial Rate Control Register (SRC)
    • 13.4.3 Serial Status and Data Register (SSD)
    • 13.4.4 Serial Input Data Register (SIDR)
    • 13.4.5 Serial Output Data Register (SODR)
    • 13.4.6 Clock Divider Selection Register (UPC)
    • 13.4.7 Serial Switch Register (SSEL)
  • 13.5 Interrupt of UART
  • 13.6 Operations of UART Functions
    • 13.6.1 Transmission Operations (Operating Mode 0, 1, 2, and 3)
    • 13.6.2 Reception Operations (Operating Mode 0, 1, or 3)
    • 13.6.3 Reception Operations (Operating Mode 2 Only)
  • 13.7 Program Example for UART
• CHAPTER 14 8-BIT SERIAL I/O
  • 14.1 Overview of 8-Bit Serial I/O
  • 14.2 Configuration of 8-Bit Serial I/O
  • 14.3 Pins of 8-Bit Serial I/O
  • 14.4 Registers of 8-Bit Serial I/O
    • 14.4.1 Serial Mode Register (SMR)
    • 14.4.2 Serial Data Register (SDR)
  • 14.5 Interrupt of 8-Bit Serial I/O
  • 14.6 Operations of Serial Output Functions
  • 14.7 Operations of Serial Input Functions
  • 14.8 8-Bit Serial I/O Operation in Each Mode
  • 14.9 Notes on Using 8-Bit Serial I/O
  • 14.10 Example of 8-Bit Serial I/O Connection
  • 14.11 Program Example for 8-Bit Serial I/O
• CHAPTER 15 BUZZER OUTPUT
  • 15.1 Overview of the Buzzer Output
  • 15.2 Configuration of the Buzzer Output
  • 15.3 Pin of the Buzzer Output
  • 15.4 Buzzer Register (BZCR)
  • 15.5 Program Example for Buzzer Output
• CHAPTER 16 WILD REGISTER FUNCTION
  • 16.1 Overview of the Wild Register Function
  • 16.2 Configuration of the Wild Register Function
  • 16.3 Registers of the Wild Register Function
    • 16.3.1 Data Setting Registers (WRDR0 and WRDR1)
    • 16.3.2 Higher Address Set Registers (WRARH0 and WRARH1)
    • 16.3.3 Lower Address Set Registers (WRARL0 and WRARL1)
    • 16.3.4 Address Comparison EN Register (WREN)
    • 16.3.5 Data Test Set Register (WROR)
  • 16.4 Operations of the Wild Register Functions
• CHAPTER 17 FLASH MEMORY
  • 17.1 Overview of Flash Memory
  • 17.2 Flash Memory Control Status Register (FMCS)
  • 17.3 Starting the Flash Memory Automatic Algorithm
  • 17.4 Confirming the Automatic Algorithm Execution State
    • 17.4.1 Data Polling Flag (DQ7)
    • 17.4.2 Toggle Bit Flag (DQ6)
    • 17.4.3 Timing Limit Exceeded Flag (DQ5)
    • 17.4.4 Toggle Bit-2 Flag (DQ2)
  • 17.5 Detailed Explanation of Writing to Erasing Flash Memory
    • 17.5.1 Setting The Read/Reset State
    • 17.5.2 Writing Data
    • 17.5.3 Erasing All Data (Erasing Chips)
  • 17.6 Flash Security Feature
  • 17.7 Notes on using Flash Memory
• APPENDIX
  • APPENDIX A I/O Map
  • APPENDIX B Overview of the Instructions
    • B.1 Addressing
    • B.2 Special Instructions
    • B.3 Bit Manipulation Instructions (SETB and CLRB)
    • B.4 F2MC-8L Instructions List
    • B.5 Instruction Map
  • APPENDIX C Mask Options
  • APPENDIX D Programming EPROM with Evaluation Chip
  • APPENDIX E Pin State of the MB89202/F202RA Series