FUJITSU F2MC-8L F202RA - Manual (Page 325)

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CHAPTER 13 UART
13.6.3 Reception Operations (Operating Mode 2 Only)
When data is received at the serial data input pin, the internal reception shift register
converts it from serial to parallel. If the data is correctly transmitted up to the stop
bit(s), data in the internal shift register is transferred to the SIDR register, then "1" is set
to the RDRF bit.
■ Reception Operations (Operating Mode 2 Only)
If an overrun error or framing error occurs, the received data is not transmitted to the SIDR register, but the
ORFE bit is set to "1".
For both RDRF and ORFE, data is fully received/transmitted with the final data bit (D8) set to "1", these
flags go on when the stop bit at the end is detected. However, when the framing error occurs, the flag goes
on regardless of the final data bit. An interrupt request to the CPU is generated when the flag goes on and
interrupt request is enabled.
If the reception interrupt is enabled (SSD: RIE = 1), an interrupt request to the CPU (IRQ5) is generated.
When the RDRF bit goes on, the received data is transmitted to the SIDR register.
Figure 13.6-7 to Figure 13.6-9 show the reception operations when parity is not used and the number of
stop bits is "1" in operating mode 2.
Figure 13.6-7 Reception Operations in Operating Mode 2
Figure 13.6-8 Operations in Operating Mode 2 when the Overrun Error Occurs
RDRF
STOP START 0 1 2 3 4 5 6 7 8
Data
Reception
interrupt
ORFE
STOP START 0 1 2 3 4 5 6 7 8
RDRF=1
Data
(reception buffer full)
Reception interrupt