FUJITSU F2MC-8L F202RA - Manual (Page 62)

46
CHAPTER 3 CPU
Note:
A reset source flag is set when a reset source is generated. When the reset source flag register is read, all
bits in the reset source flag register are cleared. Therefore, to determine the source of a reset, read this
register using the initial value setting routine after the reset.
Table 3.5-3 Explanation of Functions of Each Bit in the Reset Flag Register (RSFR)
Bit name Description
bit7
PONR:
Power-on reset flag
bit
"1" is set to this bit when power-on reset occurs.
"1" is set to this bit after power is turned on.
This bit is cleared with "0" after being read.
Writing a value to this bit has no significance.
bit6
ERST:
External reset flag bit
"1" is set to this bit when external reset occurs.
"1" is set to this bit while other reset flags are maintained when all
other reset flags have been set before the external reset flag is set.
This bit is cleared with "0" after being read.
Writing a value to this bit has no significance.
bit5
WDOG:
Watchdog reset flag
bit
"1" is set to this bit when watchdog reset occurs.
"1" is set to this bit while other reset flags are maintained when all
other reset flags have been set before the watchdog reset flag is set.
This bit is cleared with "0" after being read.
Writing a value to this bit has no significance.
bit4
SFTR:
Software reset flag
bit
"1" is set to this bit when software reset occurs.
"1" is set to this bit while other reset flags are maintained when all
other reset flags have been set before the software reset flag is set.
This bit is cleared with "0" after being read.
Writing a value to this bit has no significance.
bit3
to
bit0
Unused bits
The values read out are undefined.
Writing data to these bits does not affect operations.