FUJITSU F2MC-8L F202RA User Manual
Page 139
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123
CHAPTER 5 TIME-BASE TIMER
Figure 5.5-2 Operations of Time-base Timer
000000
H
1FFFFF
H
(TBTC:TBR=0)
Co
u
nter v
a
l
u
e
Cle
a
red
b
y
s
witching to
s
top mode
O
s
cill
a
tion
s
t
ab
iliz
a
tion
overflow
CPU
oper
a
tion
s
t
a
rt
Interv
a
l cycle
(TBTC:TBC1,TBC0=11
B)
Co
u
nter cle
a
r
Power-on re
s
et (option
a
l)
Cle
a
red
b
y interr
u
pt h
a
ndling ro
u
tine
TBOF
b
it
TBIE
b
it
S
leep
S
LP
b
it
(
S
TBC regi
s
ter)
Exit
s
top
s
t
a
te
b
y IRQ7
S
top
S
TP
b
it
(
S
TBC regi
s
ter)
Exit
s
top
s
t
a
te
b
y
a
n extern
a
l interr
u
pt
Note: When the interv
a
l time
s
election
b
it
s
of time-
bas
e timer control regi
s
ter (TBTC : TBC1, TBC0)
a
re
s
et to 11 (2
22
/F
CH
).
: O
s
cill
a
tion
s
t
ab
iliz
a
tion time
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