FUJITSU F2MC-8L F202RA - Manual (Page 65)

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CHAPTER 3 CPU
■ Mode Fetch
The CPU reads the mode data and reset vector from internal ROM following the cancellation of the reset.
●
Mode data (address: FFFD
H
)
Set single-chip mode (00
H
) to the mode data.
● Reset vector (address: FFFE
H
(highest)/FFFF
H
(lowest))
Specify the address at which execution is to be started after the reset operation is completed. The CPU
starts executing instructions from the specified address.
■ State of Reset Waiting for Stabilization of Oscillation
The CPU performs a reset operation for a reset when power is turned on or an external reset in stop mode
when the oscillation stabilization wait time specified with option settings has expired. In this case, if the
external reset input is not cancelled, the CPU performs the reset operation following cancellation of the
external reset.
When an external clock is used, oscillation stabilization wait time is applied, and thus input of an external
clock is required at a reset.
The time-base timer generates oscillation stabilization wait time.
■ Influence from a Reset of Contents in RAM
When reset conditions occur, the CPU stops handling the current instruction, then enters the reset state. The
contents in RAM does not change even after a reset. However, if a reset occurs while 16-bit data is being
written, the upper byte (only) is written; the lower byte may be unwritten. If a reset occurs immediately
after, immediately before, or while data is written, the contents in the address to which data is written at
that time is not guaranteed.