3 serial status and data register (ssd), Serial status and data register (ssd) – FUJITSU F2MC-8L F202RA User Manual
Page 310
294
CHAPTER 13 UART
13.4.3
Serial Status and Data Register (SSD)
The serial status and data register (SSD) controls data transmission/reception of UART
and status in an error, enables/disables interrupts, and specifies and checks settings
for parity or bit-8 transmitting data.
■
Serial Status and Data Register (SSD)
Figure 13.4-4 Serial Status and Data Register (SSD)
RD
8
/
RP
0
1
TD
8
/
TP
0
1
RIE
0
1
TIE
0
1
TDRE
0
1
RDRF ORFE
0
0
0
1
1
0
1
1
b
it7
b
it6
b
it5
b
it4
b
it
3
b
it2
b
it1
b
it0
002A
H
RDRF ORFE TDRE
TIE
RIE
TD
8
/TP RD
8
/RP
00100-1X
B
R
R
R/W
R/W
R/W
R/W
R
R/W
R
X
Addre
ss
Initi
a
l v
a
l
u
e
Bit-
8
receiving d
a
t
a
/p
a
rity
b
it
P
a
rity
us
ed
P
a
rity not
us
ed
(
S
MC: PEN = 1)
(
S
MC: PEN = 0)
Detect
s
odd p
a
rity.
Detect
s
even p
a
rity.
Bit-
8
receiving d
a
t
a
*
Bit-
8
tr
a
n
s
mitting d
a
t
a
/p
a
rity
b
it
P
a
rity
us
ed
(
S
MC: PEN = 1)
P
a
rity not
us
ed
(
S
MC: PEN = 0)
Add
s
odd p
a
rity.
Add
s
even p
a
rity.
S
et
s
b
it-
8
tr
a
n
s
mitting d
a
t
a
.*
Reception interr
u
pt re
qu
e
s
t en
ab
le
b
it
Di
sab
le
s
o
u
tp
u
t of reception interr
u
pt re
qu
e
s
t
s
.
En
ab
le
s
o
u
tp
u
t of reception interr
u
pt re
qu
e
s
t
s
.
Tr
a
n
s
mi
ss
ion interr
u
pt re
qu
e
s
t en
ab
le
b
it
Di
sab
le
s
o
u
tp
u
t of tr
a
n
s
mi
ss
ion interr
u
pt re
qu
e
s
t
s
.
En
ab
le
s
o
u
tp
u
t of tr
a
n
s
mi
ss
ion interr
u
pt re
qu
e
s
t
s
.
Tr
a
n
s
mitted d
a
t
a
fl
a
g
b
it
D
a
t
a
to
b
e tr
a
n
s
mitted incl
u
ded
D
a
t
a
to
b
e tr
a
n
s
mitted not incl
u
ded
Received d
a
t
a
fl
a
g
b
it/Overr
u
n/Fr
a
ming error fl
a
g
b
it
No d
a
t
a
Fr
a
ming error
Norm
a
l d
a
t
a
Overr
u
n error (previo
us
d
a
t
a
rem
a
ining)
: Re
a
d
ab
le/Writ
ab
le
: Re
a
d only
: Un
us
ed
: Undefined
: Initi
a
l v
a
l
u
e
: Effective only when d
a
t
a
length i
s
9
b
it
s
(
S
MC: MC1
a
nd MC0 = 10
B
a
nd 11
B
, oper
a
ting mode i
s
2 or
3
.)
*