Document Outline

• Intel® StrongARM® SA-1100 Microprocessor Developer's Manual
• Copyright Page
• Contents
• Figures
• Tables
• Introduction 1
  • 1.1 Intel® StrongARM® SA-1100 Microprocessor
  • 1.2 Overview
  • 1.3 Example System
  • 1.4 ARM™ Architecture
    • 1.4.1 26-Bit Mode
    • 1.4.2 Coprocessors
    • 1.4.3 Memory Management
    • 1.4.4 Instruction Cache
    • 1.4.5 Data Cache
    • 1.4.6 Write Buffer
    • 1.4.7 Read Buffer
• Functional Description 2
  • 2.1 Block Diagram
  • 2.2 Inputs/Outputs
  • 2.3 Signal Description
  • 2.4 Memory Map
• ARM™ Implementation Options 3
  • 3.1 Big and Little Endian
  • 3.2 Exceptions
    • 3.2.1 Power-Up Reset
    • 3.2.2 ROM Size Select
    • 3.2.3 Abort
    • 3.2.4 Vector Summary
    • 3.2.5 Exception Priorities
    • 3.2.6 Interrupt Latencies and Enable Timing
  • 3.3 Coprocessors
• Instruction Set 4
  • 4.1 Instruction Set
  • 4.2 Instruction Timings
• Coprocessors 5
  • 5.1 Internal Coprocessor Instructions
  • 5.2 Coprocessor 15 Definition
    • 5.2.1 Register 0 – ID
    • 5.2.2 Register 1 – Control
    • 5.2.3 Register 2 – Translation Table Base
    • 5.2.4 Register 3 – Domain Access Control
    • 5.2.5 Register 4 – RESERVED
    • 5.2.6 Register 5 – Fault Status
    • 5.2.7 Register 6 – Fault Address
    • 5.2.8 Register 7 – Cache Control Operations
    • 5.2.9 Register 8 – TLB Operations
    • 5.2.10 Register 9 – Read-Buffer Operations
    • 5.2.11 Registers 10 – 12 RESERVED
    • 5.2.12 Register 13 – Process ID Virtual Address Mapping
    • 5.2.13 Register 14 – Debug Support (Breakpoints)
    • 5.2.14 Register 15 – Test, Clock, and Idle Control
• Caches, Write Buffer, and Read Buffer 6
  • 6.1 Instruction Cache (Icache)
    • 6.1.1 Icache Operation
    • 6.1.2 Icache Validity
      • 6.1.2.1 Software Icache Flush
    • 6.1.3 Icache Enable/Disable and Reset
      • 6.1.3.1 Enabling the Icache
      • 6.1.3.2 Disabling the Icache
  • 6.2 Data Caches (Dcaches)
    • 6.2.1 Cacheable Bit – C
      • 6.2.1.1 Cacheable Reads – C = 1
      • 6.2.1.2 Noncacheable Reads – C = 0
    • 6.2.2 Bufferable Bit – B
    • 6.2.3 Software Dcache Flush
      • 6.2.3.1 Doubly Mapped Space
    • 6.2.4 Dcaches Enable/Disable and Reset
      • 6.2.4.1 Enabling the Dcaches
      • 6.2.4.2 Disabling the Dcaches
  • 6.3 Write Buffer (WB)
    • 6.3.1 Bufferable Bit
    • 6.3.2 Write Buffer Operation
      • 6.3.2.1 Writes to a Bufferable and Cacheable Location (B=1,C=1)
      • 6.3.2.2 Writes to a Bufferable and Noncacheable Location (B=1,C=0)
      • 6.3.2.3 Unbufferable Writes (B=0)
    • 6.3.3 Enabling the Write Buffer
      • 6.3.3.1 Disabling the Write Buffer
  • 6.4 Read Buffer (RB)
• Memory-Management Unit (MMU) 7
  • 7.1 Overview
    • 7.1.1 MMU Registers
  • 7.2 MMU Faults and CPU Aborts
  • 7.3 Data Aborts
    • 7.3.1 Cacheable Reads (Linefetches)
    • 7.3.2 Buffered Writes
  • 7.4 Interaction of the MMU, Icache, Dcache, and Write Buffer
  • 7.5 Mini Data Cache
• Clocks 8
  • 8.1 SA-1100 Crystal Oscillators
  • 8.2 Core Clock Configuration Register
    • 8.2.1 Restrictions on Changing the Core Clock Configuration
  • 8.3 Driving SA-1100 Crystal Pins from an External Source
  • 8.4 Clocking During Test
• System Control Module 9
  • 9.1 General-Purpose I/O
    • 9.1.1 GPIO Register Definitions
      • 9.1.1.1 GPIO Pin-Level Register (GPLR)
      • 9.1.1.2 GPIO Pin Direction Register (GPDR)
      • 9.1.1.3 GPIO Pin Output Set Register (GPSR) and Pin Output Clear Register (GPCR)
      • 9.1.1.4 GPIO Rising-Edge Detect Register (GRER) and Falling-Edge Detect Register (GFER)
      • 9.1.1.5 GPIO Edge Detect Status Register (GEDR)
      • 9.1.1.6 GPIO Alternate Function Register (GAFR)
    • 9.1.2 GPIO Alternate Functions
    • 9.1.3 GPIO Register Locations
  • 9.2 Interrupt Controller
    • 9.2.1 Interrupt Controller Register Definitions
      • 9.2.1.1 Interrupt Controller Pending Register (ICPR)
      • 9.2.1.2 Interrupt Controller IRQ Pending Register (ICIP) and FIQ Pending Register (ICFP)
      • 9.2.1.3 Interrupt Controller Mask Register (ICMR)
      • 9.2.1.4 Interrupt Controller Level Register (ICLR)
      • 9.2.1.5 Interrupt Controller Control Register (ICCR)
    • 9.2.2 Interrupt Controller Register Locations
  • 9.3 Real-Time Clock
    • 9.3.1 RTC Counter Register (RCNR)
    • 9.3.2 RTC Alarm Register (RTAR)
    • 9.3.3 RTC Status Register (RTSR)
    • 9.3.4 RTC Trim Register (RTTR)
    • 9.3.5 Trim Procedure
      • 9.3.5.1 Oscillator Frequency Calibration
      • 9.3.5.2 RTTR Value Calculations
    • 9.3.6 Real-Time Clock Register Locations
  • 9.4 Operating System Timer
    • 9.4.1 OS Timer Count Register (OSCR)
    • 9.4.2 OS Timer Match Registers 0–3 (OSMR<0>, OSMR<1>, OSMR<2>, OSMR<3>)
    • 9.4.3 OS Timer Watchdog Match Enable Register (OWER)
    • 9.4.4 OS Timer Status Register (OSSR)
    • 9.4.5 OS Timer Interrupt Enable Register (OIER)
    • 9.4.6 Watchdog Timer
    • 9.4.7 OS Timer Register Locations
  • 9.5 Power Manager
    • 9.5.1 Run Mode
    • 9.5.2 Idle Mode
      • 9.5.2.1 Entering Idle Mode
      • 9.5.2.2 Exiting Idle Mode
    • 9.5.3 Sleep Mode
      • 9.5.3.1 CPU Preparation for Sleep Mode
      • 9.5.3.2 Events Causing Entry into Sleep Mode
      • 9.5.3.3 The Sleep Shutdown Sequence
      • 9.5.3.4 During Sleep Mode
      • 9.5.3.5 The Sleep Wake-Up Sequence
      • 9.5.3.6 Booting After Sleep Mode
      • 9.5.3.7 Reviving the DRAMs from Self-Refresh Mode
    • 9.5.4 Notes on Power Supply Sequencing
    • 9.5.5 Assumed Behavior of an SA-1100 System in Sleep Mode
    • 9.5.6 Pin Operation in Sleep Mode
    • 9.5.7 Power Manager Registers
      • 9.5.7.1 Power Manager Control Register (PMCR)
      • 9.5.7.2 Power Manager General Configuration Register (PCFR)
      • 9.5.7.3 Power Manager PLL Configuration Register (PPCR)
      • 9.5.7.4 Power Manager Wake-Up Enable Register (PWER)
      • 9.5.7.5 Power Manager Sleep Status Register (PSSR)
      • 9.5.7.6 Power Manager Scratch Pad Register (PSPR)
      • 9.5.7.7 Power Manager GPIO Sleep State Register (PGSR)
      • 9.5.7.8 Power Manager Oscillator Status Register (POSR)
    • 9.5.8 Power Manager Register Locations
  • 9.6 Reset Controller
    • 9.6.1 Reset Controller Registers
      • 9.6.1.1 Reset Controller Software Reset Register (RSRR)
      • 9.6.1.2 Reset Controller Status Register (RCSR)
    • 9.6.2 Reset Controller Register Locations
• Memory and PCMCIA Control Module 10
  • 10.1 Overview of Operation
    • 10.1.1 Example Memory System
    • 10.1.2 Types of Memory Accesses
    • 10.1.3 Reads
    • 10.1.4 Writes
    • 10.1.5 Transaction Summary
    • 10.1.6 Read-Lock-Write
    • 10.1.7 Aborts and Nonexistent Memory
  • 10.2 Memory Configuration Registers
    • 10.2.1 DRAM Configuration Register (MDCNFG)
    • 10.2.2 DRAM CAS Waveform Shift Registers (MDCAS0, MDCAS1, MDCAS2)
    • 10.2.3 Static Memory Control Registers (MSC1–0)
    • 10.2.4 Expansion Memory (PCMCIA) Configuration Register (MECR)
  • 10.3 Dynamic Interface Operation
    • 10.3.1 DRAM Overview
    • 10.3.2 DRAM Timing
    • 10.3.3 DRAM Refresh
    • 10.3.4 DRAM Self-Refresh in Sleep Mode
  • 10.4 Static Memory Interface
    • 10.4.1 ROM Interface Overview
    • 10.4.2 ROM Timing Diagrams and Parameters
    • 10.4.3 SRAM Interface Overview
    • 10.4.4 SRAM Timing Diagrams and Parameters
    • 10.4.5 FLASH EPROM Interface Overview
    • 10.4.6 FLASH EPROM Timing Diagrams and Parameters
  • 10.5 General Memory BUS Timing
    • 10.5.1 Static Access Followed by a DRAM Access
    • 10.5.2 DRAM Access Followed by a Static Access
    • 10.5.3 DRAM Access Followed by a Refresh Operation
  • 10.6 PCMCIA Overview
    • 10.6.1 32-Bit Data Bus Operation
    • 10.6.2 External Logic for PCMCIA Implementation
    • 10.6.3 PCMCIA Interface Timing Diagrams and Parameters
  • 10.7 Initialization of the Memory Interface
    • 10.7.1 Flow of Events After Reset or Exiting Sleep Mode
  • 10.8 Alternate Memory Bus Master Mode
• Peripheral Control Module 11
  • 11.1 Read/Write Interface
  • 11.2 Memory Organization
  • 11.3 Interrupts
  • 11.4 Peripheral Pins
  • 11.5 Use of the GPIO Pins for Alternate Functions
  • 11.6 DMA Controller
    • 11.6.1 DMA Register Definitions
      • 11.6.1.1 DMA Device Address Register (DDARn)
      • 11.6.1.2 DMA Control/Status Register (DCSRn)
      • 11.6.1.3 DMA Buffer A Start Address Register (DBSAn)
      • 11.6.1.4 DMA Buffer A Transfer Count Register (DBTAn)
      • 11.6.1.5 DMA Buffer B Start Address Register (DBSBn)
      • 11.6.1.6 DMA Buffer B Transfer Count Register (DBTBn)
    • 11.6.2 DMA Operation
    • 11.6.3 DMA Register List
  • 11.7 LCD Controller
    • 11.7.1 LCD Controller Operation
      • 11.7.1.1 DMA to Memory Interface
      • 11.7.1.2 Frame Buffer
      • 11.7.1.3 Input FIFO
      • 11.7.1.4 Lookup Palette
      • 11.7.1.5 Color/Gray-Scale Dithering
      • 11.7.1.6 Output FIFO
      • 11.7.1.7 LCD Controller Pins
    • 11.7.2 LCD Controller Register Definitions
    • 11.7.3 LCD Controller Control Register 0
      • 11.7.3.1 LCD Enable (LEN)
      • 11.7.3.2 Color/Monochrome Select (CMS)
      • 11.7.3.3 Single-/Dual-Panel Select (SDS)
      • 11.7.3.4 LCD Disable Done Interrupt Mask (LDM)
      • 11.7.3.5 Base Address Update Interrupt Mask (BAM)
      • 11.7.3.6 Error Interrupt Mask (ERM)
      • 11.7.3.7 Passive/Active Display Select (PAS)
      • 11.7.3.8 Big/Little Endian Select (BLE)
      • 11.7.3.9 Double-Pixel Data (DPD) Pin Mode
      • 11.7.3.10 Palette DMA Request Delay (PDD)
    • 11.7.4 LCD Controller Control Register 1
      • 11.7.4.1 Pixels Per Line (PPL)
      • 11.7.4.2 Horizontal Sync Pulse Width (HSW)
      • 11.7.4.3 End-of-Line Pixel Clock Wait Count (ELW)
      • 11.7.4.4 Beginning-of-Line Pixel Clock Wait Count (BLW)
    • 11.7.5 LCD Controller Control Register 2
      • 11.7.5.1 Lines Per Panel (LPP)
      • 11.7.5.2 Vertical Sync Pulse Width (VSW)
      • 11.7.5.3 End-of-Frame Line Clock Wait Count (EFW)
      • 11.7.5.4 Beginning-of-Frame Line Clock Wait Count (BFW)
    • 11.7.6 LCD Controller Control Register 3
      • 11.7.6.1 Pixel Clock Divider (PCD)
      • 11.7.6.2 AC Bias Pin Frequency (ACB)
      • 11.7.6.3 AC Bias Pin Transitions Per Interrupt (API)
      • 11.7.6.4 Vertical Sync Polarity (VSP)
      • 11.7.6.5 Horizontal Sync Polarity (HSP)
      • 11.7.6.6 Pixel Clock Polarity (PCP)
      • 11.7.6.7 Output Enable Polarity (OEP)
    • 11.7.7 LCD Controller DMA Registers
    • 11.7.8 DMA Channel 1 Base Address Register
    • 11.7.9 DMA Channel 1 Current Address Register
    • 11.7.10 DMA Channel 2 Base and Current Address Registers
    • 11.7.11 LCD Controller Status Register
      • 11.7.11.1 LCD Disable Done Flag (LDD) (read/write, maskable interrupt)
      • 11.7.11.2 Base Address Update Flag (BAU) (read-only, maskable interrupt)
      • 11.7.11.3 Bus Error Status (BER) (read/write, maskable interrupt)
      • 11.7.11.4 AC Bias Count Status (ABC) (read/write, nonmaskable interrupt)
      • 11.7.11.5 Input FIFO Overrun Lower Panel Status (IOL) (read/write, maskable interrupt)
      • 11.7.11.6 Input FIFO Underrun Lower Panel Status (IUL) (read/write, maskable interrupt)
      • 11.7.11.7 Input FIFO Overrun Upper Panel Status (IOU) (read/write, maskable interrupt)
      • 11.7.11.8 Input FIFO Underrun Upper Panel Status (IUU) (read/write, maskable interrupt)
      • 11.7.11.9 Output FIFO Overrun Lower Panel Status (OOL) (read/write, maskable interrupt)
      • 11.7.11.10 Output FIFO Underrun Lower Panel Status (OUL) (read/write, maskable interrupt)
      • 11.7.11.11 Output FIFO Overrun Upper Panel Status (OOU) (read/write, maskable interrupt)
      • 11.7.11.12 Output FIFO Underrun Upper Panel Status (OUU) (read/write, maskable interrupt)
    • 11.7.12 LCD Controller Register Locations
    • 11.7.13 LCD Controller Pin Timing Diagrams
  • 11.8 Serial Port 0 – USB Device Controller
    • 11.8.1 USB Operation
      • 11.8.1.1 Signalling Levels
      • 11.8.1.2 Bit Encoding
      • 11.8.1.3 Field Formats
      • 11.8.1.4 Packet Formats
      • 11.8.1.5 Transaction Formats
      • 11.8.1.6 UDC Device Requests
    • 11.8.2 UDC Register Definitions
    • 11.8.3 UDC Control Register
      • 11.8.3.1 UDC Disable (UDD)
      • 11.8.3.2 UDC Active (UDA)
      • 11.8.3.3 Bit 2 Reserved
      • 11.8.3.4 Endpoint 0 Interrupt Mask (EIM)
      • 11.8.3.5 Receive Interrupt Mask (RIM)
      • 11.8.3.6 Transmit Interrupt Mask (TIM)
      • 11.8.3.7 Suspend/Resume Interrupt Mask (SRM)
      • 11.8.3.8 Reset Interrupt Mask (REM)
    • 11.8.4 UDC Address Register
    • 11.8.5 UDC OUT Max Packet Register
    • 11.8.6 UDC IN Max Packet Register
    • 11.8.7 UDC Endpoint 0 Control/Status Register
      • 11.8.7.1 OUT Packet Ready (OPR)
      • 11.8.7.2 IN Packet Ready (IPR)
      • 11.8.7.3 Sent Stall (SST)
      • 11.8.7.4 Force Stall (FST)
      • 11.8.7.5 Data End (DE)
      • 11.8.7.6 Setup End (SE)
      • 11.8.7.7 Serviced OPR (SO)
      • 11.8.7.8 Serviced Setup End (SSE)
    • 11.8.8 UDC Endpoint 1 Control/Status Register
      • 11.8.8.1 Receive FIFO Service (RFS)
      • 11.8.8.2 Receive Packet Complete (RPC)
      • 11.8.8.3 Receive Packet Error (RPE)
      • 11.8.8.4 Sent Stall (SST)
      • 11.8.8.5 Force Stall (FST)
      • 11.8.8.6 Receive FIFO Not Empty (RNE)
      • 11.8.8.7 Bits 7..6 Reserved
    • 11.8.9 UDC Endpoint 2 Control/Status Register
      • 11.8.9.1 Transmit FIFO Service (TFS)
      • 11.8.9.2 Transmit Packet Complete (TPC)
      • 11.8.9.3 Transmit Packet Error (TPE)
      • 11.8.9.4 Transmit Underrun (TUR)
      • 11.8.9.5 Sent STALL (SST)
      • 11.8.9.6 Force STALL (FST)
      • 11.8.9.7 Bits 7..6 Reserved
    • 11.8.10 UDC Endpoint 0 Data Register
    • 11.8.11 UDC Endpoint 0 Write Count Register
    • 11.8.12 UDC Data Register
    • 11.8.13 UDC Status/Interrupt Register
      • 11.8.13.1 Endpoint 0 Interrupt Request (EIR)
      • 11.8.13.2 Receive Interrupt Request (RIR)
      • 11.8.13.3 Transmit Interrupt Request (TIR)
      • 11.8.13.4 Suspend Interrupt Request (SUSIR)
      • 11.8.13.5 Resume Interrupt Request (RESIR)
      • 11.8.13.6 Reset Interrupt Request (RSTIR)
    • 11.8.14 UDC Register Locations
  • 11.9 Serial Port 1 – SDLC/UART
    • 11.9.1 SDLC Operation
      • 11.9.1.1 Bit Encoding
      • 11.9.1.2 Frame Format
      • 11.9.1.3 Address Field
      • 11.9.1.4 Control Field
      • 11.9.1.5 Data Field
      • 11.9.1.6 CRC Field
      • 11.9.1.7 Baud Rate Generation
      • 11.9.1.8 Receive Operation
      • 11.9.1.9 Transmit Operation
      • 11.9.1.10 Simultaneous Use of the UART and SDLC
      • 11.9.1.11 Transmit and Receive FIFOs
      • 11.9.1.12 CPU and DMA Register Access Sizes
    • 11.9.2 SDLC Register Definitions
    • 11.9.3 SDLC Control Register 0
      • 11.9.3.1 SDLC/UART Select (SUS)
      • 11.9.3.2 Single/Double Flag Select (SDF)
      • 11.9.3.3 Loopback Mode (LBM)
      • 11.9.3.4 Bit Modulation Select (BMS)
      • 11.9.3.5 Sample Clock Enable (SCE)
      • 11.9.3.6 Sample Clock Direction (SCD)
      • 11.9.3.7 Receive Clock Edge Select (RCE)
      • 11.9.3.8 Transmit Clock Edge Select (TCE)
    • 11.9.4 SDLC Control Register 1
      • 11.9.4.1 Abort After Frame (AAF)
      • 11.9.4.2 Transmit Enable (TXE)
      • 11.9.4.3 Receive Enable (RXE)
      • 11.9.4.4 Receive FIFO Interrupt Enable (RIE)
      • 11.9.4.5 Transmit FIFO Interrupt Enable (TIE)
      • 11.9.4.6 Address Match Enable (AME)
      • 11.9.4.7 Transmit FIFO Underrun Select (TUS)
      • 11.9.4.8 Receiver Abort Interrupt Enable(RAE)
    • 11.9.5 SDLC Control Register 2
      • 11.9.5.1 Address Match Value (AMV)
    • 11.9.6 SDLC Control Registers 3 and 4
      • 11.9.6.1 Baud Rate Divisor (BRD)
    • 11.9.7 SDLC Data Register
    • 11.9.8 SDLC Status Register 0
      • 11.9.8.1 End/Error in FIFO Status (EIF) (read-only, nonmaskable interrupt)
      • 11.9.8.2 Transmit Underrun Status (TUR) (read/write, maskable interrupt)
      • 11.9.8.3 Receiver Abort Status (RAB) (read/write, maskable interrupt)
      • 11.9.8.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)
      • 11.9.8.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt)
    • 11.9.9 SDLC Status Register 1
      • 11.9.9.1 Receiver Synchronized Flag (RSY) (read-only, noninterruptible)
      • 11.9.9.2 Transmitter Busy Flag (TBY) (read-only, noninterruptible)
      • 11.9.9.3 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)
      • 11.9.9.4 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)
      • 11.9.9.5 Receive Transition Detect Status (RTD) (read/write, noninterruptible)
      • 11.9.9.6 End of Frame Flag (EOF) (read-only, noninterruptible)
      • 11.9.9.7 CRC Error Status (CRE) (read-only, noninterruptible)
      • 11.9.9.8 Receiver Overrun Status (ROR) (read-only, noninterruptible)
    • 11.9.10 UART Register Locations
    • 11.9.11 SDLC Register Locations
  • 11.10 Serial Port 2 – Infrared Communications Port (ICP)
    • 11.10.1 Low-Speed ICP Operation
      • 11.10.1.1 HP-SIR* Modulation
      • 11.10.1.2 UART Frame Format
    • 11.10.2 High-Speed ICP Operation
      • 11.10.2.1 4PPM Modulation
      • 11.10.2.2 HSSP Frame Format
      • 11.10.2.3 Address Field
      • 11.10.2.4 Control Field
      • 11.10.2.5 Data Field
      • 11.10.2.6 CRC Field
      • 11.10.2.7 Baud Rate Generation
      • 11.10.2.8 Receive Operation
      • 11.10.2.9 Transmit Operation
      • 11.10.2.10 Transmit and Receive FIFOs
      • 11.10.2.11 CPU and DMA Register Access Sizes
    • 11.10.3 UART Register Definition
    • 11.10.4 UART Control Register 4
      • 11.10.4.1 HP-SIR Enable (HSE)
      • 11.10.4.2 Low-Power Mode (LPM)
    • 11.10.5 HSSP Register Definitions
    • 11.10.6 HSSP Control Register 0
      • 11.10.6.1 IrDA Transmission Rate (ITR)
      • 11.10.6.2 Loopback Mode (LBM)
      • 11.10.6.3 Transmit FIFO Underrun Select (TUS)
      • 11.10.6.4 Transmit Enable (TXE)
      • 11.10.6.5 Receive Enable (RXE)
      • 11.10.6.6 Receive FIFO Interrupt Enable (RIE)
      • 11.10.6.7 Transmit FIFO Interrupt Enable (TIE)
      • 11.10.6.8 Address Match Enable (AME)
    • 11.10.7 HSSP Control Register 1
      • 11.10.7.1 Address Match Value (AMV)
    • 11.10.8 HSSP Control Register 2
      • 11.10.8.1 Transmit Pin Polarity Select (TXP)
      • 11.10.8.2 Receive Pin Polarity Select (RXP)
    • 11.10.9 HSSP Data Register
    • 11.10.10 HSSP Status Register 0
      • 11.10.10.1 End/Error in FIFO Status (EIF) (read-only, nonmaskable interrupt)
      • 11.10.10.2 Transmit Underrun Status (TUR) (read/write, maskable interrupt)
      • 11.10.10.3 Receiver Abort Status (RAB) (read/write, nonmaskable interrupt)
      • 11.10.10.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)
      • 11.10.10.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt)
      • 11.10.10.6 Framing Error Status (FRE) (read/write, nonmaskable interrupt)
    • 11.10.11 HSSP Status Register 1
      • 11.10.11.1 Receiver Synchronized Flag (RSY) (read-only, noninterruptible)
      • 11.10.11.2 Transmitter Busy Flag (TBY) (read-only, noninterruptible)
      • 11.10.11.3 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)
      • 11.10.11.4 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)
      • 11.10.11.5 End-of-Frame Flag (EOF) (read-only, noninterruptible)
      • 11.10.11.6 CRC Error Status (CRE) (read-only, noninterruptible)
      • 11.10.11.7 Receiver Overrun Status (ROR) (read-only, noninterruptible)
    • 11.10.12 UART Register Locations
    • 11.10.13 HSSP Register Locations
  • 11.11 Serial Port 3 - UART
    • 11.11.1 UART Operation
      • 11.11.1.1 Frame Format
      • 11.11.1.2 Baud Rate Generation
      • 11.11.1.3 Receive Operation
      • 11.11.1.4 Transmit Operation
      • 11.11.1.5 Transmit and Receive FIFOs
      • 11.11.1.6 CPU and DMA Register Access Sizes
    • 11.11.2 UART Register Definitions
    • 11.11.3 UART Control Register 0
      • 11.11.3.1 Parity Enable (PE)
      • 11.11.3.2 Odd/Even Parity Select (OES)
      • 11.11.3.3 Stop Bit Select (SBS)
      • 11.11.3.4 Data Size Select (DSS)
      • 11.11.3.5 Sample Clock Enable (SCE)
      • 11.11.3.6 Receive Clock Edge Select (RCE)
      • 11.11.3.7 Transmit Clock Edge Select (TCE)
    • 11.11.4 UART Control Registers 1 and 2
      • 11.11.4.1 Baud Rate Divisor (BRD)
    • 11.11.5 UART Control Register 3
      • 11.11.5.1 Receiver Enable (RXE)
      • 11.11.5.2 Transmitter Enable (TXE)
      • 11.11.5.3 Break (BRK)
      • 11.11.5.4 Receive FIFO Interrupt Enable (RIE)
      • 11.11.5.5 Transmit FIFO Interrupt Enable (TIE)
      • 11.11.5.6 Loopback Mode (LBM)
    • 11.11.6 UART Data Register
    • 11.11.7 UART Status Register 0
      • 11.11.7.1 Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)
      • 11.11.7.2 Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt)
      • 11.11.7.3 Receiver Idle Status (RID) (read/write, maskable interrupt)
      • 11.11.7.4 Receiver Begin of Break Status (RBB) (read/write, nonmaskable interrupt)
      • 11.11.7.5 Receiver End of Break Status (REB) (read/write, nonmaskable interrupt)
      • 11.11.7.6 Error in FIFO Flag (EIF) (read-only, nonmaskable interrupt)
    • 11.11.8 UART Status Register 1
      • 11.11.8.1 Transmitter Busy Flag (TBY) (read-only, noninterruptible)
      • 11.11.8.2 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)
      • 11.11.8.3 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)
      • 11.11.8.4 Parity Error Flag (PRE) (read-only, noninterruptible)
      • 11.11.8.5 Framing Error Flag (FRE) (read-only, noninterruptible)
      • 11.11.8.6 Receiver Overrun Flag (ROR) (read-only, noninterruptible)
    • 11.11.9 UART Register Locations
  • 11.12 Serial Port 4 – MCP / SSP
    • 11.12.1 MCP Operation
      • 11.12.1.1 Frame Format
      • 11.12.1.2 Audio and Telecom Sample Rates and Data Transfer
      • 11.12.1.3 MCP Transmit and Receive FIFO Operation
      • 11.12.1.4 Codec Control Register Data Transfer
      • 11.12.1.5 External Clock Operation
      • 11.12.1.6 Alternate SSP Pin Assignment
      • 11.12.1.7 CPU and DMA Register Access Sizes
    • 11.12.2 MCP Register Definitions
    • 11.12.3 MCP Control Register
      • 11.12.3.1 Audio Sample Rate Divisor (ASD)
      • 11.12.3.2 Telecom Sample Rate Divisor (TSD)
      • 11.12.3.3 Multimedia Communications Port Enable (MCE)
      • 11.12.3.4 External Clock Select (ECS)
      • 11.12.3.5 A/D Sampling Mode (ADM)
      • 11.12.3.6 Telecom Transmit FIFO Interrupt Enable (TTE)
      • 11.12.3.7 Telecom Receive FIFO Interrupt Enable (TRE)
      • 11.12.3.8 Audio Transmit FIFO Interrupt Enable (ATE)
      • 11.12.3.9 Audio Receive FIFO Interrupt Enable (ARE)
      • 11.12.3.10 Loopback Mode (LBM)
      • 11.12.3.11 External Clock Prescaler (ECP)
    • 11.12.4 MCP Control Register 1
      • 11.12.4.1 Clock Frequency Select (CFS)
    • 11.12.5 MCP Data Registers
      • 11.12.5.1 MCP Data Register 0
      • 11.12.5.2 MCP Data Register 1
      • 11.12.5.3 MCP Data Register 2
    • 11.12.6 MCP Status Register
      • 11.12.6.1 Audio Transmit FIFO Service Request Flag (ATS) (read-only, maskable interrupt)
      • 11.12.6.2 Audio Receive FIFO Service Request Flag (ARS) (read-only, maskable interrupt)
      • 11.12.6.3 Telecom Transmit FIFO Service Request Flag (TTS) (read-only, maskable interrupt)
      • 11.12.6.4 Telecom Receive FIFO Service Request Flag (TRS) (read-only, maskable interrupt)
      • 11.12.6.5 Audio Transmit FIFO Underrun Status (ATU) (read/write, nonmaskable interrupt)
      • 11.12.6.6 Audio Receive FIFO Overrun Status (ARO) (read/write, nonmaskable interrupt)
      • 11.12.6.7 Telecom Transmit FIFO Underrun Status (TTU) (read/write, nonmaskable interrupt)
      • 11.12.6.8 Telecom Receive FIFO Overrun Status (TRO) (read/write, nonmaskable interrupt)
      • 11.12.6.9 Audio Transmit FIFO Not Full Flag (ANF) (read-only, noninterruptible)
      • 11.12.6.10 Audio Receive FIFO Not Empty Flag (ANE) (read-only, noninterruptible)
      • 11.12.6.11 Telecom Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)
      • 11.12.6.12 Telecom Receive FIFO Not Empty Flag (TNE) (read-only, noninterruptible)
      • 11.12.6.13 Codec Write Completed Flag (CWC) (read-only, noninterruptible)
      • 11.12.6.14 Codec Read Completed Flag (CRC) (read-only, noninterruptible)
      • 11.12.6.15 Audio Codec Enabled Flag (ACE) (read-only, noninterruptible)
      • 11.12.6.16 Telecom Codec Enabled Flag (TCE) (read-only, noninterruptible)
    • 11.12.7 SSP Operation
      • 11.12.7.1 Frame Format
      • 11.12.7.2 Baud Rate Generation
      • 11.12.7.3 SSP Transmit and Receive FIFOs
      • 11.12.7.4 CPU and DMA Register Access Sizes
      • 11.12.7.5 Alternate SSP Pin Assignment
    • 11.12.8 SSP Register Definitions
    • 11.12.9 SSP Control Register 0
      • 11.12.9.1 Data Size Select (DSS)
      • 11.12.9.2 Frame Format (FRF)
      • 11.12.9.3 Synchronous Serial Port Enable (SSE)
      • 11.12.9.4 Serial Clock Rate (SCR)
    • 11.12.10 SSP Control Register 1
      • 11.12.10.1 Receive FIFO Interrupt Enable (RIE)
      • 11.12.10.2 Transmit FIFO Interrupt Enable (TIE)
      • 11.12.10.3 Loopback Mode (LBM)
      • 11.12.10.4 Serial Clock Polarity (SPO)
      • 11.12.10.5 Serial Clock Phase (SPH)
      • 11.12.10.6 External Clock Select (ECS)
    • 11.12.11 SSP Data Register
    • 11.12.12 SSP Status Register
      • 11.12.12.1 Transmit FIFO Not Full Flag (TNF) (read-only, noninterruptible)
      • 11.12.12.2 Receive FIFO Not Empty Flag (RNE) (read-only, noninterruptible)
      • 11.12.12.3 SSP Busy Flag (BSY) (read-only, noninterruptible)
      • 11.12.12.4 Transmit FIFO Service Request Flag (TFS) (read-only, maskable interrupt)
      • 11.12.12.5 Receive FIFO Service Request Flag (RFS) (read-only, maskable interrupt)
      • 11.12.12.6 Receiver Overrun Status (ROR) (read/write, nonmaskable interrupt)
    • 11.12.13 MCP Register Locations
    • 11.12.14 SSP Register Locations
  • 11.13 Peripheral Pin Controller (PPC)
    • 11.13.1 PPC Operation
    • 11.13.2 PPC Register Definitions
    • 11.13.3 PPC Pin Direction Register
    • 11.13.4 PPC Pin State Register
    • 11.13.5 PPC Pin Assignment Register
      • 11.13.5.1 UART Pin Reassignment (UPR)
      • 11.13.5.2 SSP Pin Reassignment (SPR)
    • 11.13.6 PPC Sleep Mode Pin Direction Register
    • 11.13.7 PPC Pin Flag Register
    • 11.13.8 PPC Register Locations
• DC Parameters 12
  • 12.1 Absolute Maximum Ratings
  • 12.2 DC Operating Conditions
  • 12.3 Power Supply Voltages and Currents
• AC Parameters 13
  • 13.1 Test Conditions
  • 13.2 Module Considerations
  • 13.3 Memory Bus and PCMCIA Signal Timings
  • 13.4 LCD Controller Signals
  • 13.5 MCP Signals
  • 13.6 Timing Parameters
    • 13.6.1 Asynchronous Signal Timing Descriptions
• Package and Pinout 14
  • 14.1 Mechanical Data and Packaging Information
  • 14.2 Mini-Ball Grid Array – (mBGA)
• Debug Support 15
  • 15.1 Instruction Breakpoint
  • 15.2 Data Breakpoint
• Boundary-Scan Test Interface 16
  • 16.1 Overview
  • 16.2 Reset
  • 16.3 Pull-Up Resistors
  • 16.4 Instruction Register
  • 16.5 Public Instructions
    • 16.5.1 EXTEST (00000)
    • 16.5.2 SAMPLE/PRELOAD (00001)
    • 16.5.3 CLAMP (00100)
    • 16.5.4 HIGHZ (00101)
    • 16.5.5 IDCODE (00110)
    • 16.5.6 BYPASS (11111)
  • 16.6 Test Data Registers
    • 16.6.1 Bypass Register
    • 16.6.2 SA-1100 Device Identification (ID) Code Register
    • 16.6.3 SA-1100 Boundary-Scan (BS) Register
  • 16.7 Boundary-Scan Interface Signals
• Register Summary A
• 3.6864–MHz Oscillator Specifications B
  • B.1 Specifications
    • B.1.1 System Specifications
      • B.1.1.1. Parasitic Capacitance Off-chip Between PXTAL and PEXTAL
      • B.1.1.2. Parasitic Capacitance Off-chip Between PXTAL or PEXTAL and VSS
      • B.1.1.3. Parasitic Resistance Between PXTAL and PEXTAL
      • B.1.1.4. Parasitic Resistance Between PXTAL or PEXTAL and VSS
    • B.1.2 Quartz Crystal Specification
• 32.768–kHz Oscillator Specifications C
  • C.1 Specifications
    • C.1.1 System Specifications
      • C.1.1.1. Temperature Range
      • C.1.1.2. Current Consumption
      • C.1.1.3. Startup Time
      • C.1.1.4. Frequency Shift Due to Temperature Effect on the Circuit
      • C.1.1.5. Parasitic Capacitance Off-chip Between TXTAL and TEXTAL
      • C.1.1.6. Parasitic Capacitance Off-chip Between TXTAL or TEXTAL and VSS
      • C.1.1.7. Parasitic Resistance Between TXTAL and TEXTAL
      • C.1.1.8. Parasitic Resistance Between TXTAL or TEXTAL and VSS
    • C.1.2 Quartz Crystal Specification
• Internal Test D
  • D.1 Test Unit Control Register (TUCR)
• Support, Products, and Documentation