8 serviced setup end (sse), 8serviced setup end (sse) -69 – Intel STRONGARM SA-1100 User Manual
Page 219
SA-1100 Developer’s Manual
11-69
Peripheral Control Module
11.8.7.8
Serviced Setup End (SSE)
The serviced setup end bit will clear the SE bit (5) when writing a one.
Address: 0h 8000 0010
UDCCS0
Read/Write
Bit
7
6
5
4
3
2
1
0
SSE
SO
SE
DE
FST
SST
IPR
OPR
Reset
0
0
0
0
0
0
0
0
Bit
Name
Description
0
OPR
OUT packet ready (read-only).
1 – OUT packet ready.
1
IPR
IN packet ready (read/write 1 to set).
1 – IN packet ready.
2
SST
Sent stall (read/write 1 to clear).
1 – UDC sent stall handshake.
3
FST
Force stall (read/write 1 to set).
1 – Force stall handshake.
4
DE
Data end (read/write 1 to set).
1 – The last byte of the data phase has been written.
5
SE
Setup end (read-only).
1 – Control transfer ended before data end got set.
6
SO
Serviced OPR (write-only).
1 – Clear OPR, bit 0.
7
SSE
Serviced setup end (write-only).
1 – Clear SE, bit 5.