Intel STRONGARM SA-1100 - Manual (Page 5)

SA-1100 Developer’s Manual v
9 System Control Module ...................................................................................................9-1
9.1 General-Purpose I/O.......................................................................................... 9-1
9.1.1
GPIO Register Definitions..................................................................... 9-2
9.1.1.1 GPIO Pin-Level Register (GPLR) ............................................ 9-3
9.1.1.2 GPIO Pin Direction Register (GPDR) ...................................... 9-4
9.1.1.3 GPIO Pin Output Set Register (GPSR) and
Pin Output Clear Register (GPCR) .......................................... 9-5
9.1.1.4 GPIO Rising-Edge Detect Register (GRER) and
Falling-Edge Detect Register (GFER) ..................................... 9-6
9.1.1.5 GPIO Edge Detect Status Register (GEDR)............................ 9-7
9.1.1.6 GPIO Alternate Function Register (GAFR) .............................. 9-8
9.1.2 GPIO Alternate Functions..................................................................... 9-9
9.1.3 GPIO Register Locations .................................................................... 9-10
9.2 Interrupt Controller........................................................................................... 9-11
9.2.1
Interrupt Controller Register Definitions.............................................. 9-11
9.2.1.1 Interrupt Controller Pending Register (ICPR) ........................ 9-12
9.2.1.2 Interrupt Controller IRQ Pending Register (ICIP) and
FIQ Pending Register (ICFP)................................................. 9-13
9.2.1.3 Interrupt Controller Mask Register (ICMR) ............................ 9-14
9.2.1.4 Interrupt Controller Level Register (ICLR) ............................. 9-15
9.2.1.5 Interrupt Controller Control Register (ICCR).......................... 9-16
9.2.2 Interrupt Controller Register Locations ............................................... 9-17
9.3 Real-Time Clock .............................................................................................. 9-17
9.3.1
RTC Counter Register (RCNR) .......................................................... 9-17
9.3.2 RTC Alarm Register (RTAR) .............................................................. 9-18
9.3.3 RTC Status Register (RTSR).............................................................. 9-18
9.3.4 RTC Trim Register (RTTR)................................................................. 9-19
9.3.5 Trim Procedure ................................................................................... 9-19
9.3.5.1 Oscillator Frequency Calibration............................................ 9-19
9.3.5.2 RTTR Value Calculations ...................................................... 9-20
9.3.6 Real-Time Clock Register Locations .................................................. 9-21
9.4 Operating System Timer.................................................................................. 9-21
9.4.1
OS Timer Count Register (OSCR)...................................................... 9-22
9.4.2 OS Timer Match Registers 0–3
OSMR<0>, OSMR<1>, OSMR<2>, OSMR<3>)................................. 9-22
9.4.3 OS Timer Watchdog Match Enable Register (OWER) ....................... 9-22
9.4.4 OS Timer Status Register (OSSR) ..................................................... 9-23
9.4.5 OS Timer Interrupt Enable Register (OIER) ....................................... 9-24
9.4.6 Watchdog Timer ................................................................................. 9-24
9.4.7 OS Timer Register Locations.............................................................. 9-25
9.5 Power Manager .............................................................................................. 9-26
9.5.1
Run Mode ........................................................................................... 9-26
9.5.2 Idle Mode ............................................................................................ 9-26
9.5.2.1 Entering Idle Mode................................................................. 9-26
9.5.2.2 Exiting Idle Mode ................................................................... 9-27
9.5.3 Sleep Mode......................................................................................... 9-27
9.5.3.1 CPU Preparation for Sleep Mode .......................................... 9-27
9.5.3.2 Events Causing Entry into Sleep Mode ................................. 9-27
9.5.3.3 The Sleep Shutdown Sequence ............................................ 9-28
9.5.3.4 During Sleep Mode ................................................................ 9-28
9.5.3.5 The Sleep Wake-Up Sequence ............................................. 9-28