3 spi (master mode) timing diagrams, Figure 35, Spi (master mode) output ac timing diagram – Marvel Group Integrated Controller 88F6281 User Manual

Page 112: Figure 36, Spi (master mode) input ac timing diagram

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88F6281
Hardware Specifications

Doc. No. MV-S104859-U0 Rev. E

Copyright © 2008 Marvell

Page 112

Document Classification: Proprietary Information

December 2, 2008, Preliminary

8.6.12.3

SPI (Master Mode) Timing Diagrams

Figure 35: SPI

(Master Mode)

Output AC Timing Diagram

Figure 36: SPI

(Master Mode)

Input AC Timing Diagram

SCLK

tCL

tCH

Data

Out

CS

tDOVmax

tDOVmin

tCSB

tCSA

tSU

SCLK

Data in

tHD

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