Figure 7, Figure 8, Sdram ddr2 interface read ac timing diagram – Marvel Group Integrated Controller 88F6281 User Manual

Page 92

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88F6281
Hardware Specifications

Doc. No. MV-S104859-U0 Rev. E

Copyright © 2008 Marvell

Page 92

Document Classification: Proprietary Information

December 2, 2008, Preliminary

Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram

Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram

ADDRESS/

CONTROL

tIPW

tAOVB

tAOVA

CLKn

CLK

tCL

tCH

tDHI

tDSI

DQ

DQS

DQSn

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