Motorola DSP56301 User Manual
Page 194
HI32 Programming Model/Quick Reference
6
-76
DSP56301 User’s Manual
DPMC
15-0
AR[31–16] DSP PCI Transaction
Address (High)
written only if
MARQ = 1
$0000
-
-
21-16
BL[5–0]
PCI Data Burst Length
written only if
MARQ = 1
$0
-
-
23-22
FC[1–0]
Data Transfer Format
Control
00
01
10
11
Transmit
Receive
32 bit mode
32 bit mode
3 Right, zero ext
.3 LSBs
3 Right, sign ext
.3 LSBs
3 Left, zero filled
3 MSBs
written only if
MARQ = 1
$0
-
-
DPAR
15-0
AR[15–0] DSP PCI Transaction
Address (Low)
written only if
MARQ = 1
$0000
-
-
19-16
C[3–0]
PCI Bus Command
written only if
MARQ = 1
$0
-
-
23-20
BE[3–0]
PCI Byte Enables
written only if
MARQ = 1
$0
-
-
DSR
0
HCP
Host Command
Pending
0
1
no host command pending
host command pending
cleared when
the HC interrupt
request is
serviced
-
-
0
1
STRQ
Slave Transmit Data
Request
1
0
slave transmit FIFO is not full
slave transmit FIFO is full
cleared if the
DTXS is filled by
core writes
1
1
-
1
2
SRRQ
Slave Receive Data
Request
0
1
slave receive FIFO is empty
slave receive FIFO is not
empty
cleared if the
DRXR is
emptied by core
reads or the
data to be read
from the DRXR
is master data
0
-
0
5-3
HF[2–0]
Host Flags
-
$0
-
23
HACT
HI32 Active
0
1
HI32 is in personal reset (PS)
HI32 is active
0
-
0
DPSR
0
MWS
PCI Master Wait
States
0
1
HI32 is asserting HIRDY
HI32 is deasserting HIRDY
0
-
0
1
MTRQ
PCI Master Transmit
Data Request
1
0
master transmit FIFO is not
full
master transmit FIFO is full
cleared if the
DTXM is filled by
core writes
1
-
1
2
MRRQ
PCI Master
Receive Data Request
0
1
master receive FIFO is empty
master receive FIFO is not
empty
cleared if the
DRXR is
emptied by core
reads or the
data to be read
from the DRXR
is slave data.
0
-
0
4
MARQ
PCI Master Address
Request
1
0
Core can initiate new
transaction
Core cannot initiate new
transaction
0
0
0
HI32 Registers—Quick Reference
Reg
Bit
Comments
Reset Type
Num
Mnemonic
Name
Val
Function
HS
PH
PS