Motorola DSP56301 - Manual (Page 363)

Index -7
DSP PCI Transaction Address (High)
(AR[31–16]) 6-32
PCI Data Burst Length (BL[5–0]) 6-32
DSP PCI Port Control Register (DPCR) 6-26
Clear Transmitter (CLRT) 6-29
HSERR Force (SERF) 6-28
Insert Address Enable (IAE) 6-27
Master Access Counter Enable (MACE) 6-28
Master Address Interrupt Enable (MAIE) 6-30
Master Receive Interrupt Enable (MRIE) 6-30
Master Transfer Terminate (MTT) 6-28
Master Transmit Interrupt Enable (MTIE) 6-30
Master Wait State Disable (MWSD) 6-28
Parity Error Interrupt Enable (PEIE) 6-29
Receive Buffer Lock Enable (RBLE) 6-27
Transaction Abort Interrupt Enable (TAIE) 6-29
Transaction Termination Interrupt Enable
(TTIE) 6-29
Transfer Complete Interrupt Enable (TCIE) 6-29
DSP PCI Status Register (DPSR) 6-38
Master Data Transferred (MDT) 6-39
PCI Address Parity Error (APER) 6-40
PCI Data Parity Error (DPER) 6-40
PCI Host Data Transfer Complete (HDTC) 6-39
PCI Master Abort (MAB) 6-40
PCI Master Address Request (MARQ) 6-40
PCI Master Receive Data Request (MRRQ) 6-41
PCI Master Transmit Data Request
(MTRQ) 6-41
PCI Master Wait States (MWS) 6-41
PCI Target Abort (TAB) 6-40
PCI Target Disconnect (TDIS) 6-40
PCI Target Retry (TRTY) 6-39
PCI Time Out Termination (TO) 6-39
Remaining Data Count (RDC[5–0]) 6-38
Remaining Data Count Qualifier (RDCQ) 6-38
DSP Receive Data FIFO (DRXR) 6-41
DSP Slave Transmit Data Register (DTXS) 6-7
, 6-42
DSP Status Register (DSR) 6-35
HI32 Active (HACT) 6-35
Host Command Pending (HCP) 6-37
Host Flags 2–0 (HF[2–0]) 6-36
Slave Receive Data Request (SRRQ) 6-36
Slave Transmit Data Request (STRQ) 6-37
DSP56300 core access 6-22
DSP-side
operating modes 6-12
programming model 6-22
DSP-to-host
data path 6-7
general-purpose flags 6-26
enable/disable master access counter 6-28
Enhanced Universal Bus mode 6-15
examples of host-to-HI32 connections 6-18
exception handlers 6-6
external data buffer 6-4
GPIO 5-5
, 6-16
GPIO mode 6-13 , 6-16
HAD[31–0) pins 6-33
handshake flags 6-44
Header Type/Latency Timer Configuration Register
(CHTY/CLAT/CCLS) 6-68
Cache Line Size (CLS[7–0]) 6-69
Header Type (HT[7–0]) 6-68
Header Type (HT[7–0])) 6-68
Latency Timer (High) (LT[7–0]) 6-69
HI32 Control Register (HCTR) 6-48
DMA Enable (DMAE) 6-54
Host Flags 2–0 (HF[2–0]) 6-54
Host Receive Data Transfer Format
(HRF[1–0]) 6-50
Host Semaphores (HS[2–0]) 6-49
Host Transmit Data Transfer Format
(HTF[1–0]) 6-51
Receive Request Enable (RREQ) 6-55
Slave Fetch Type (SFT) 6-52
Target Wait State Disable (TWSD) 6-49
Transmit Request Enable (TREQ) 6-56
HI32 Mode (HM) bits 6-12
HI32-to-memory data transfers 6-22
HI32-to-PCI agent data transfers 6-45
host command 6-6
Host Command Vector Register (HCVR) 6-59
Host Command (HC) 6-61
Host Command Vector (HV[6–0]) 6-60
Host Non-Maskable Interrupt (HNMI) 6-60
Host Data Direction Register (HDDR)
programming sheet B-40
Host Data Register (HDR)
programming sheet B-40
Host Interface Control Register (HCTR) 6-6
Host Interface Status Register (HSTR) 6-57
Host Flags 5–3 (HF[5–3]) 6-57
Host Interrupt A (HINT) 6-57
Host Receive Data Request (HRRQ) 6-58
Host Request (HREQ) 6-57
Host Transmit Data Request (HTRQ) 6-58
Transmitter Ready (TRDY) 6-58
Host Master Receive Data Register (HRXM) 6-7 ,
6-61
Host Port Pins 2-16
host request 6-57
Host Slave Receive Data Register (HRXS) 6-61
, 6-62
Host Transmit Data Register (HTXR) 6-62
host-side
programming model 6-44
HTXR-DRXR and DTXM-HRXM data paths 6-6
incomplete burst 6-38