Motorola DSP56301 - Manual (Page 359)

Index -3
Debug mode
entering 2-29
external indication 2-29
Debug support 1-5
Detected Parity Error (DPE) bit 6-65
Device/Vendor ID Configuration Register
(CDID/CVID) 6-64
DEVSEL Timing (DST[1–0]) bits 6-65
Direct Memory Access (DMA)
ISA/EISA bus 6-15
ISA/EISA bus enable 6-54
Request Source bits 4-29
techniques 6-22
transfers 5-2
, 5-4
triggered by timer 9-25
Direction (DIR) bit 9-30
Division Factor (DF) bits 4-21
DMA Address Mode (DAM) bit 4-34
DMA Channel Enable (DE) bit 4-29
DMA Channel Priority (DPR) bit 4-31
DMA Continuous Mode Enable (DCON) bit 4-32
DMA Control Registers (DCRs) 4-29
bit definitions 4-29
DMA Address Mode (DAM) 4-34
DMA Channel Enable (DE) 4-29
DMA Channel Priority (DPR) 4-31
DMA Continuous Mode Enable (DCON) 4-32
DMA Destination Space (DDS) 4-34
DMA Interrupt Enable (DIE) 4-30
DMA Request Source (DRS) 4-33
DMA Source Space (DSS) 4-34
DMA Three-Dimensional Mode (D3D) 4-33
DMA Transfer Mode (DTM) 4-30
programming sheet B-21
DMA Destination Space (DDS) bit 4-34
DMA Enable (DMAE) bit 6-54
DMA Enable (ISA/EISA) bit 6-54
DMA Interrupt Enable (DIE) bit 4-30
DMA Request Source (DRS) bit 4-33
DMA see Direct Memory Access
DMA Source Space (DSS) bit 4-34
DMA Three-Dimensional Mode (D3D) bit 4-33
DMA Transfer Mode (DTM) bit 4-30
DO FOREVER (FV) Flag bit 4-8
DO loop 1-4
, 1-8
Do Loop Flag (LF) bit 4-8
document conventions 1-2
Double-Precision Multiply Mode (DM) bit 4-9
DRAM
controller 1-5
DRAM Control Register (DCR) 4-22 , 4-24
Bit Definitions 4-25
Bus Column In-Page Wait State (BCW) 4-26
Bus DRAM Page Size (BPS) 4-26
Bus Mastership Enable (BME) 4-25
Bus Page Logic Enable (BPLE) 4-26
Bus Refresh Enable (BREN) 4-25
Bus Refresh Prescaler (BRP) 4-25
Bus Refresh Rate (BRF) 4-25
Bus Row Out-of-Page Wait States (BRW) 4-26
Bus Software Triggered Reset (BSTR) 4-25
programming sheet B-19
DSP Control Register (DCTR) 6-12
Host Command Interrupt Enable (HCIE) 6-26
Host Data Strobe Mode (HDSM) 6-25
Host DMA Request Polarity (HDRP) 6-24
Host Flags 5–3 (HF[5–3]) 6-26
Host Interrupt A (HINT) 6-25
Host Interrupt Request Drive Control (HIRD) 6-24
Host Interrupt Request Handshake Mode
(HIRH) 6-24
Host Read/Write Polarity (HRWP) 6-25
Host Reset Polarity (HRSP) 6-24
Host Transfer Acknowledge Polarity (HTAP) 6-25
Slave Receive Interrupt Enable (SRIE) 6-26
Slave Transmit Interrupt Enable (STIE) 6-26
DSP Host Port GPIO Data Register (DATH) 6-43
DSP Master Transmit Data Register (DTXM) 6-42
DSP PCI Address Register (DPAR)
DSP PCI Transaction Address (Low)
(AR[15–0]) 6-34
PCI Bus Command (C[3–0]) 6-34
PCI Byte Enables (BE[3–0]) 6-33
DSP PCI Master Control Register (DPMC)
Data Transfer Format Control (FC[1–0]) 6-31
DSP PCI Transaction Address (High)
(AR[31–16]) 6-32
PCI Data Burst Length (BL[5–0]) 6-32
DSP PCI Port Control Register (DPCR)
Clear Transmiter (CLRT) 6-29
HSERR Force (SERF) 6-28
Insert Address Enable (IAE) 6-27
Master Access Counter Enable (MACE) 6-28
Master Address Interrupt Enable (MAIE) 6-30
Master Receive Interrupt Enable (MRIE) 6-30
Master Transfer Terminate (MTT) 6-28
Master Transmit Interrupt Enable (MTIE) 6-30
Master Wait State Disable (MWSD) 6-28
Parity Error Interrupt Enable (PEIE) 6-29
Receive Buffer Lock Enable (RBLE) 6-27
Transaction Abort Interrupt Enable (TAIE) 6-29
Transaction Termination Interrupt Enable
(TTIE) 6-29
Transfer Complete Interrupt Enable (TCIE) 6-29
DSP PCI Status Register (DPSR)
Master Data Transferred (MDT) 6-39
PCI Address Parity Error (APER) 6-40
PCI Data Parity Error (DPER) 6-40