Spectrum Brands MC.31XX - Manual (Page 56)

56 MC.31xx Manual
Programming FIFO Mode
FIFO mode
In normal applications the FIFO mode will run in a loop and process one buffer after the other. There are a few special commands and reg-
isters for the FIFO mode:
The start command and the wait command both wait for the signal from the driver that the next buffer has to be processed. This signal is
generated by the driver on receiving an interrupt from the hardware. While waiting none of these commands waiste cpu power (no polling
mode). If for any reason the signal is not coming from the hardware (e.g. trigger is not found) the FIFO mode must be stopped from a second
task with a stop command.
This handshake command tells the driver that the application has finished it’s work with the software buffer. The both commands
SPC_FIFOWAIT (SPC_FIFOSTART) and SPC_FIFO_BUFFERS form a simple but powerful handshake protocol between application software
and board driver.
Backward compatibility: This register replaces the formerly known SPC_FIFO_BUFREADY0 ...
SPC_FIFO_BUFREADY15 commands. It has the same functionality but can handle more FIFO buffers. For back-
ward compatibility the older commands still work but are still limited to 16 buffers.
Example FIFO acquisition mode
This example shows the main loop of a FIFO acquisition. The example is a part of the FIFO examples that are available for each board on
CD. The example simply counts the buffers when it receives a new buffer from the driver and returns control immideately back to the driver.
FIFO acquisition example:
Data organization
When using FIFO mode data in memory is organized in some cases a little bit different then in standard mode. This is a result of the internal
hardware structure of the board. The organization of data is depending on the activated channels:
The samples are re-named for better readability. A0 is sample 0 of channel 0, C4 is sample 4 of channel 2, ...
Register Value Direction Description
SPC_COMMAND 0 w Command register. Allowed values for FIFO mode are listed below
SPC_FIFOSTART 12 Starts the FIFO mode and waits for the first interrupt
SPC_FIFOWAIT 13 Waits for the next buffer interrupt
SPC_STOP 20 Stops the FIFO mode
Register Value Direction Description
SPC_FIFO_BUFREADY 60050 w FIFO mode handshake. Application has finsihed with that buffer. Value is index of buffer
nBufIdx = 0;
lBufCount = 0;
lCommand = SPC_FIFOSTART;
printf ("Start\n");
do
{
nErr = SpcSetParam (hDrv, SPC_COMMAND, lCommand);
lCommand = SPC_FIFOWAIT;
// ----- perform any data calculation or hard disk recording (in example only counting buffers)-----
printf ("FIFO Buffer %ld\n", lBufCount++);
// ----- buffer is ready -----
SpcSetParam (hDrv, SPC_FIFO_BUFREADY, nBufIdx);
// ----- next Buffer -----
nBufIdx++;
if (nBufIdx == MAX_BUF)
nBufIdx = 0;
}
while (nErr == ERR_OK);
Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Sample ordering in FIFO buffer
X A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
X X A0 E0 A1 E1 A2 E2 A3 E3 A4 E4 A5 E5 A6 E6 A7 E7
X X A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7
X X X X A0 E0 B0 F0 A1 E1 B1 F1 A2 E2 B2 F2 A3 E3 B3 F3
X X X X A0 B0 C0 D0 A1 B1 C1 D1 A2 B2 C2 D2 A3 B3 C3 D3
X X X X X X X X A0 E0 B0 F0 C0 G0 D0 H0 A1 E1 B1 F1 C1 G1 D1 H1