Resulting start delays, Number of samples on gate signal, Allowed trigger modes – Spectrum Brands MC.31XX User Manual
Page 81
Option Gated Sampling
Trigger modes
(c) Spectrum GmbH
81
Resulting start delays
Number of samples on gate signal
As described above there’s a delay at the start of the gate interval due to the internal memory structure. However this delay can be partly
compensated by internal pipelines resulting in a data delay that even can be negative showing the trigger event (acquisition mode only). This
data delay is listed in an extra table. But beneath this compensation there’s still the start delay that as a result causes the card to use less
samples than the gate signal length. Please refer to the following table to see how many samples less than the length of gate signal are used
Allowed trigger modes
As mentioned above not all of the possible trigger modes can be used as a gate condition. The following table is showing the allowed trigger
modes that can be used and explains the event that has to be detected for gate-start end for gate-end.
External TTL edge trigger
The following table shows the allowed trigger modes when using the external TTL trigger connector:
External TTL pulsewidth trigger
The following table shows the allowed pulsewidth trigger modes when using the external TTL trigger connector:
Sample rate
Activated channels
external TTL trigger
internal trigger
ext. TTL trigger with
activated
synchronization
internal trigger with
activated
synchronization
0
1
2
3
4
5
6
7
< 5 MS/s
x
-4 samples
+4 samples
-3 samples
+5 samples
> 5 MS/s
x
+4 samples
+16 samples
+5 samples
+17 samples
< 5 MS/s
x
x
-4 samples
+4 samples
-3 samples
+5 samples
> 5 MS/s
x
x
+4 samples
+16 samples
+5 samples
+17 samples
< 2.5 MS/s
x
x
-4 samples
+4 samples
-3 samples
+5 samples
> 2.5 MS/s
x
x
+2 samples
+10 samples
+3 samples
+11 samples
< 2.5 MS/s
x
x
x
x
-4 samples
+4 samples
-3 samples
+5 samples
> 2.5 MS/s
x
x
x
x
+2 samples
+10 samples
+3 samples
+11 samples
< 1.25 MS/s
x
x
x
x
-4 samples
+5 samples
-4 samples
+5 samples
> 1.25 MS/s
x
x
x
x
-1 samples
+8 samples
-1 samples
+9 samples
< 1.25 MS/s
x
x
x
x
x
x
x
x
-4 samples
+5 samples
-4 samples
+5 samples
> 1.25 MS/s
x
x
x
x
x
x
x
x
-1 samples
+8 samples
-1 samples
+9 samples
Module 0
Module 1
0
1
2
3
0
1
2
3
Mode
Sampling clock
less samples
Sampling clock less samples
X
Standard/FIFO
< 5 MS/s
7
> 5 MS/s
12
X
X
Standard
< 5 MS/s
7
> 5 MS/s
12
X
X
FIFO
< 2.5 MS/s
3
> 2.5 MS/s
6
X
X
Standard/FIFO
< 2.5 MS/s
3
> 2.5 MS/s
6
X
X
X
X
Standard
< 2.5 MS/s
3
> 2.5 MS/s
6
X
X
X
X
FIFO
< 1.25 MS/s
2
> 1.25 MS/s
3
X
X
X
X
Standard/FIFO
< 1.25 MS/s
2
> 1.25 MS/s
3
X
X
X
X
X
X
X
X
Standard
< 1.25 MS/s
2
> 1,25 MS/s
3
X
X
X
X
X
X
X
X
FIFO
< 625 kS/s
1
> 625 kS/s
2
Mode
Gate start will be detected on
Gate end will be detected on
TM_TTLPOS
positive edge on external trigger
negative edge on external trigger
TM_TTL_NEG
negative edge on external trigger
positive edge on external trigger
Mode
Gate start will be detected on
Gate end will be detected on
TM_TTLHIGH_LP
high pulse of external trigger longer than programmed pulsewidth
negative edge on external trigger
TM_TTLLOW_LP
low pulse of external trigger longer than programmed pulsewidth
positive edge on external trigger