Sun Microsystems Sun Fire X4240 - Manual (Page 43)

Appendix A Event Logs and POST Codes 33
POST Code Checkpoints
The POST code checkpoints are the largest set of checkpoints during the BIOS pre-
boot process.
TABLE A-2 describes the type of checkpoints that might occur during
the POST portion of the BIOS. These two-digit checkpoints are the output from
primary I/O port 80.
TABLE A-2 POST Code Checkpoints
Post Code Description
03 Disable NMI, Parity, video for EGA, and DMA controllers. At this point, only ROM
accesses go to the GPNV. If BB size is 64K, turn on ROM Decode below FFFF0000h. It
should allow USB to run in the E000 segment. The HT must program the NB specific
initialization and OEM specific initialization, and can program if it need be at beginning of
BIOS POST, similar to overriding the default values of kernel variables.
04 Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is
OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is
bad, update CMOS with power-on default values and clear passwords. Initialize status
register A. Initialize data variables that are based on CMOS setup questions. Initialize both
the 8259-compatible PICs in the system.
05 Initialize the interrupt controlling hardware (generally PIC) and interrupt vector table.
06 Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch
handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to
“POSTINT1ChHandlerBlock.”
C0 Early CPU Init Start--Disable Cache--Init Local APIC.
C1 Set up boot strap processor information.
C2 Set up boot strap processor for POST. This includes frequency calculation, loading BSP
microcode, and applying user requested value for GART Error Reporting setup question.
C3 Errata workarounds applied to the BSP (#78 & #110).
C5 Enumerate and set up application processors. This includes microcode loading and
workarounds for errata (#78, #110, #106, #107, #69, #63).
C6 Re-enable cache for boot strap processor, and apply workarounds in the BSP for errata
#106, #107, #69, and #63 if appropriate. In case of mixed CPU steppings, errors are sought
and logged, and an appropriate frequency for all CPUs is found and applied. NOTE: APs
are left in the CLI HLT state.
C7 The HT sets link frequencies and widths to their final values. This routine gets called after
CPU frequency has been calculated to prevent bad programming.
0A Initializes the 8042 compatible Keyboard Controller.
0B Detects the presence of PS/2 mouse.
0C Detects the presence of Keyboard in KBC port.