Mds-s50 – Sony MDS-S50 User Manual
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MDS-S50
Pin No.
Pin Name
I/O
Description
32
XINT
I
Interrupt status input from the CXD2662R (IC151)
33
BEEP
O
Beep sound drive signal output
Headphone muting on/off control signal output “L”: muting on, “H”: muting off
(Used for the except US and Canadian model)
34
LRCKI
O
L/R sampling clock signal (44.1 kHz) output to the CXD2662R (IC151)
35
WRPWR
O
Laser power selection signal output to the CXD2662R (IC151) and HF module switch circuit
“L”: playback mode, “H”: recording mode
36
I2CCLK
I/O
Serial data transfer clock signal input/output terminal for the IIC bus
37
I2CDAT
I/O
Serial data input/output terminal for the IIC bus
38
SWDT
O
Writing serial data signal output to the CXD2662R (IC151)
39
VCC
—
Power supply terminal (+3.3V)
40
SRDT
I
Reading serial data signal input from the CXD2662R (IC151)
41
VSS
—
Ground terminal
42
SCLK
O
Serial data transfer clock signal output to the CXD2662R (IC151)
43
REC-SW
I
Detection signal input from the recording position of over write head (HR901) detect switch
(S105) “L” recording mode
44
TX0 (CLIP)
O
Serial data output to the CXD2662R (IC151)
45
RX0 (CLIP)
I
Serial data input
46
CLK (CLIP)
O
Bit clock signal (2.8224 MHz) output to the CXD2662R (IC151)
47
DIG-RST
O
Reset signal output to the CXD2662R (IC151) and BH6511FS (IC141) “L”: reset
48
SENS
I
Internal status (SENSE) input from the CXD2662R (IC151)
49
PLAY-SW
I
Detection signal input from the playback position of over write head (HR901) detect switch
(S104) “L” playback mode
50
XLATCH
O
Serial data latch pulse signal output to the CXD2662R (IC151)
51
OUT-SW
I
Detection signal input from the loading-out detect switch (S103)
“L” at a load-out position, others: “H”
52
RDY
O
Not used (open)
53
ALE
O
Not used (open)
54
HOLD
O
Not used (open)
55
HLDA
O
Not used (open)
56
MNT2 (XBUSY)
I
Busy monitor signal input from the CXD2662R (IC151)
57
VSS
—
Ground terminal
58
MNT1 (SHOCK)
I
Track jump detection signal input from the CXD2662R (IC151)
59
VCC
—
Power supply terminal (+3.3V)
60
EEP-WP
O
Writing protect signal output to the EEPROM (IC195)
61
SDA
I/O
Two-way data bus with the EEPROM (IC195)
62
BCLK
O
Not used (open)
63
OE
O
Data reading strobe signal output to the flash memory “L” active Not used (open)
64
BHE
O
Not used (open)
65
WE
O
Writing enable signal output to the flash memory “L” active Not used (open)
66
SCL
O
Clock signal output to the EEPROM (IC195)
67
REFLECT SW
I
Detection signal input from the disc reflection rate detect switch (S102-1)
“L”: high reflection rate disc, “H”: low reflection rate disc
68
PROTECT SW
I
REC-proof claw detection signal input from the protect detect switch (S102-2)
“H”: write protect
69 to 71
CS0 to CS2
O
Chip select signal output to the flash memory “L” active Not used (open)
72, 73
A20, A19
O
Address signal output to the flash memory Not used (open)
74
VCC
—
Power supply terminal (+3.3V)
75
A18
O
Address signal output to the flash memory Not used (open)