Pci connector j1 (back), Table 3.3 – LSI 20160 User Manual

Page 44

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3-6

Technical Specifications

Copyright © 2001 by LSI Logic Corporation. All rights reserved.

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Table 3.3

PCI Connector J1 (Back)

1

1. Shaded lines are not connected.

Signal Name

Pin

Signal Name

Pin

TRST

2

2. Active LOW signal.

1

AD16

32

+12 V

2

+3.3 V

33

TMS

3

FRAME

2

34

TDI

4

GND

35

+5 V

5

TRDY

2

36

INTA

2

6

GND

37

INTC

2

7

STOP

2

38

+5 V

8

+3.3 V

39

RESERVED

9

SDONE

40

3 V/5 V

10

SBO

2

41

RESERVED

11

GND

42

KEYWAY

12

PAR

43

KEYWAY

13

AD15

44

RESERVED

14

+3.3 V

45

RST

2

15

AD13

46

3 V/5 V

16

AD11

47

GNT

2

17

GND

48

GND

18

AD09

49

RESERVED

19

KEYWAY

50

AD30

20

KEYWAY

51

+3.3 V

21

C_BE0

2

52

AD28

22

+3.3 V

53

AD26

23

AD06

54

GND

24

AD04

55

AD24

25

GND

56

IDSEL

26

AD02

57

+3.3 V

27

AD00

58

AD22

28

3 V/5 V

59

AD20

29

REQ64

2

60

GND

30

+5 V

61

AD18

31

+5 V

62

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