Renesas Emulator Debugger M16C PC4701 - Manual (Page 21)

1 Features
7
1.3.2 Trace Condition Setting
The following designations are available as trace events:
•
Address designation
-
Instruction fetch
- Memory access
- Bit access
• External trigger designation (eight events)
• Interruption
The number of events that can be specified are six events of all. These break events can be combined
as below:
•
Trace when all of the valid events are established (AND condition)
• Trace when all of the valid events are established at the same time (And(same time) comdition)
• Trace when one of the valid events is established (OR condition)
• Trace upon entering a break state during state transition (State Transition condition)
You can select "specified task only" (or "other than specified task") as the trace condition to meet the
real time OS.
1.3.3 Trace Data Write Condition
Trace data write conditions can be specified.
You can specify the following write conditions:
•
Write conditions unlimited (default)
• Cycles from the start event established to the end event established
• Only cycles where the start event is established
• Cycles from the start event established to the start event unestablished
• Other than cycles from the start event established to the end event established
• Other than cycles where the start event is established
• Other than cycles from the start event established to the start event unestablished