A.14 timer_b registers, word access (continued) – Texas Instruments MSP430x1xx User Manual
Page 349
Timer_B Registers, Word Access (Continued)
A-17
Peripheral File Map
A.14 Timer_B Registers, Word Access (Continued)
Bit # –
15
14
13
12
11
10
9
8
Timer_B interrupt vector
TBIV 11Eh
0
r0
0
r0
0
r0
0
r0
0
r0
0
r0
0
r0
0
r0
Bit # –
7
6
5
4
3
2
1
0
Timer_B interrupt vector
0
0
0
0
TBIV
0
Timer_B interru t vector
TBIV 11Eh
0
r0
0
r0
0
r0
0
r0
r-(0)
r-(0)
r-(0)
0
r0
TBIV Vector, Timer_B5 (five capture/compare blocks integrated)
0:
2:
4:
6:
8:
10:
12:
14:
No interrupt pending
CCIFG1 flag set, interrupt flag of capture/compare block 1
CCIFG2 flag set, interrupt flag of capture/compare block 2 (CCIFG1=0)
CCIFG3 flag set, interrupt flag of capture/compare block 3 (CCIFG1=CCIFG2=0)
CCIFG4 flag set, interrupt flag of capture/compare block 4 (CCIFG1=CCIFG2=CCIFG3=0)
CCIFG5 flag set, interrupt flag of capture/compare block 5 (CCIFG1=CCIFG2=CCIFG3=CCIFG4=0)
CCIFG6 flag set, interrupt flag of capture/compare block 6 (CCIFG1=CCIFG2=CCIFG3=CCIFG4=CCIFG5=0)
TBIFG flag set, interrupt flag of Timer_B register/counter
(CCIFG1=CCIFG2=CCIFG3=CCIFG4=CCIFG5=CCIFG6=0)
TBIV Vector, Timer_B3 (three capture/compare blocks integrated)
0:
2:
4:
6:
8:
10:
12:
14:
No interrupt pending
CCIFG1 flag set, interrupt flag of capture/compare block 1
CCIFG2 flag set, interrupt flag of capture/compare block 2 (CCIFG1=0)
Reserved
Reserved
Reserved
Reserved
TBIFG flag set, interrupt flag of Timer_B register/counter (CCIFG1=CCIFG2=0)