Texas Instruments MSP430x1xx - Manual (Page 61)

RAM and Peripheral Organization
4-9
Memory
Table 4–1. Peripheral File Address Map—Word Modules
Address Description
1F0h – 1FFh Reserved
1E0h – 1EFh Reserved
1D0h – 1DFH Reserved
1C0h – 1CFH Reserved
1B0h – 1BFH Reserved
1A0h – 1AFH ADC12 control and interrupt
190h – 19FH Timer_B
180h – 18FH Timer_B
170h – 17FH Timer_A
160h – 16FH Timer_A
150h – 15FH ADC12 conversion
140h – 14FH ADC12 conversion
130h – 13FH Multiplier
120h – 12FH Watchdog Timer, Flash control
110h – 11FH Reserved
100h – 10FH Reserved
4.4.2.2 Byte Modules
Byte modules are peripherals that are connected to the reduced (eight LSB)
MDB. Access to byte modules is always by byte instructions. The hardware
in the peripheral byte modules takes the low byte (the LSBs) during a write
operation.
Byte instructions operate on byte modules without any restrictions. Read
access to peripheral byte modules using word instructions results in
unpredictable data in the high byte. Word data is written into a byte module by
writing the low byte to the appropriate peripheral register and ignoring the high
byte.
The peripheral file address space is organized into sixteen frames as
described in Table 4–2.