Texas Instruments MSP430x1xx - Manual (Page 137)

The Watchdog Timer
9-5
Watchdog Timer
9.1.2 Watchdog Timer Interrupt Control Functions
The Watchdog Timer (WDT) uses two bits in the SFRs for interrupt control.
- The WDT interrupt flag (WDTIFG) (located in IFG1.0, initial state is reset)
- The WDT interrupt enable (WDTIE) (located in IE1.0, initial state is reset)
When using the watchdog mode, the WDTIFG flag is used by the reset
interrupt service routine to determine if the watchdog caused the device to
reset. If the flag is set, then the Watchdog Timer initiated the reset condition
(either by timing out or by a security key violation). If the flag is cleared, then
the PUC was caused by a different source. See chapter 3 for more details on
the PUC and POR signals.
When using the Watchdog Timer in interval-timer mode, the WDTIFG flag is
set after the selected time interval and a watchdog interval-timer interrupt is
requested. The interrupt vector address in interval-timer mode is different from
that in watchdog mode. In interval-timer mode, the WDTIFG flag is reset
automatically when the interrupt is serviced.
The WDTIE bit is used to enable or disable the interrupt from the Watchdog
Timer when it is being used in interval-timer mode. Also, the GIE bit enables
or disables the interrupt from the Watchdog Timer when it is being used in
interval-timer mode.
9.1.3 Watchdog Timer Operation
The WDT module can be configured in two modes: watchdog and the interval-
timer modes.
9.1.3.1 Watchdog Mode
When the WDT is configured to operate in watchdog mode, both a watchdog
overflow and a security violation trigger the PUC signal, which automatically
clears the appropriate system register bits. This results in a system
configuration for the WDTCTL bits where the WDT is set into the watchdog
mode and the RST/NMI pin is switched to the reset configuration.
After a power-on reset or a system reset, the WDT module automatically
enters the watchdog mode and all bits in the WDTCTL register and the
watchdog counter (WDTCNT) are cleared. The initial conditions at register
WDTCTL cause the WDT to start running at a relatively-low frequency, due to
the range of the digitally-controlled oscillator (DCO) automatically being set in
these situations. Since the WDTCNT is reset, the user software has ample
time to set up or halt the WDT and to adjust the system frequency. Users must
refer to the specific data sheets and the clock-system chapter of this manual
to determine the details of the clocking circuit on the MSP430 device chosen.