Texas Instruments MSP430x1xx - Manual (Page 56)

Internal ROM Organization
4-4
4.3 Internal ROM Organization
Various sizes of ROM (OTP, masked-ROM, EPROM, or FLASH) are available
within the 64-kB address space, as shown in Figure 4–4. The common
address space is shared with SFRs, peripheral module registers, data and
code memory. The SFRs and peripheral modules are mapped into the address
range, starting with 0 and ending with 01FFh. The remaining address space,
0200h to 0FFFFh, is shared by data and code memory. The start address for
ROM depends on the amount of ROM present. The interrupt vector table is
mapped into the the upper 16 words of ROM address space, with the highest
priority interrupt vector at the highest ROM word address (0FFFEh). See the
individual data sheets for specific memory maps.
Figure 4–4. ROM Organization
4 k
12 k
0FFFEh
0F000h
0EFFFh
0D000h
0CFFFh
08000h
32 k
xx k
Vectors Vectors Vectors Vectors Vectors
0FFE0h
4.3.1 Processing of ROM Tables
The MSP430 architecture allows for the storage and usage of large tables in
ROM without the need to copy the tables to RAM before using them. This ROM
accessing of tables allows fast and clear programming in applications where
data tables are necessary. This offers the flexible advantages listed below, and
saves on ROM and RAM requirements. To access these tables, all word and
byte instructions can be used.
- ROM storage of an output programmable logic array (OPLA) for display
character conversion
- The use of as many OPLA terms as needed (no restriction on n terms)
- OTP version automatically includes OPLA programmability
- Computed table accessibility (for example, for a bar graph display)
- Table-supported program flows