Texas Instruments MSP50C614 - Manual (Page 399)

Architecture
A-5 MSP50C605 Preliminary Data
Figure A–2. MSP50C605 Memory Organization
0x0000
0x0800
0x07FF
0x7FF0
0x7FF7
User ROM
30704 x 17 bit
(C605 : read–only)
(P614 : EPROM)
Internal Test Code
2048 x 17 bit
(reserved )
Program Memory Peripheral Ports
0x 027F
0x 0000
Data Memory
RAM
640 x 17 bit
0x 00 DRD
0–7
Macro Call Vectors
255 x 17 bit
(overlaps interrupt vector
locations)
0x 08 DRP
0–3
0x 10 PC
0..7
data
0x 20
PC
0..7
ctrl
0x 24
PD
0..7
data
0x 28
PD
0..7
ctrl
0x 2C
PE
0..7
data
0x 30
PE
0..7
ctrl
0x 34
PF
0..7
data
0x 38
DRA
0–15
0x 39
DAC data
0x 3A
DAC ctrl
0x 3B
IntGenCtrl
IFR
0x 3D
PRD1
0x 3E
TIM1
0x 3F
0x 14
ClkSpdCtrl
0x 18
PRD2
0x 1C
TIM2
0x7F00
0x 2F RTRIM
Usable Interrupt
Vectors
8 x 17 bit
0x7FFE
Unusable Interrupt
Vectors
(reserved)
0x7FF8
RESET vector 0x7FFF
DATA ROM
(slow)
229,376 x 8 bit
0x 00000
0x 38000
Data ROM