Texas Instruments MSP50C614 - Manual (Page 54)

Interrupt Logic
2-24
Note: Setting a Bit in the IFR Using the OUT Instruction
Setting a bit within the IFR using the OUT instruction is a valid way of obtain-
ing a software interrupt. An IFR bit may also be cleared, using OUT, at any
time.
Assuming the global interrupt enable is set and the specific bit within the IMR
is set, then, at the time of the interrupt-trigger event, an interrupt service
branch is initiated. (The trigger event is marked by a 0-to-1 transition in the IFR
bit). At that time, the core processor searches all interrupt levels which have
both: 1) pending interrupt flag, and 2) interrupt service enabled. The highest
priority interrupt among these is selected. The program then branches to the
location which is stored in the associated Interrupt Vector (Section 2.6.3,
Inter-
rupt Vectors). This location constitutes the start of the interrupt service routine.
Instructions in the interrupt service routine are executed until the IRET (return)
instruction is encountered. Afterwards, any other pending interrupts will be
similarly serviced, in the order of their priority. Eventually, the program returns
to whatever point it was before the first interrupt service branch.
When an interrupt service branch is taken, the global interrupt enable is
automatically cleared by the core processor. This disables all further interrupt
service branches while still in the pending service routine. As a result, the
programmer must re-enable the interrupts globally using the INTE instruction.
If performed as the second-to-last instruction in the service routine, then no
nesting of multiple interrupts will occur. If, on the other hand, a nesting of
certain interrupts is desired, then the INTE instruction may be included as the
first instruction (or anywhere else) within the service routine.
When an interrupt service branch is taken, the processor core also clears
another status, namely, the respective bit in the IFR. This action automatically
communicates to the IFR that the current pending interrupt is now being
serviced. Once cleared, the IFR bit is ready to receive another SET whenever
the next trigger event occurs for that interrupt.
Note: Interrupt Service Branch
If the interrupt service branch is not enabled by the respective bit in the mask
register, then neither the global interrupt enable nor the respective flag bit is
cleared. No program vectoring occurs.