Xilinx SP601 Hardware UG518 - Manual (Page 21)

SP601 Hardware User Guide www.xilinx.com 21
UG518 (v1.1) August 19, 2009
Detailed Description
H16 FLASH_A6 23 A6
H15 FLASH_A7 22 A7
H14 FLASH_A8 20 A8
H13 FLASH_A9 19 A9
F18 FLASH_A10 18 A10
F17 FLASH_A11 17 A11
K13 FLASH_A12 13 A12
K12 FLASH_A13 12 A13
E18 FLASH_A14 11 A14
E16 FLASH_A15 10 A15
G13 FLASH_A16 8 A16
H12 FLASH_A17 7 A17
D18 FLASH_A18 6 A18
D17 FLASH_A19 5 A19
G14 FLASH_A20 4 A20
F14 FLASH_A21 3 A21
C18 FLASH_A22 1 A22
C17 FLASH_A23 30 A23
F16 FLASH_A24 56 A24
R13 FPGA_D0_DIN_MISO_MISO1 33 DQ0
T14 FPGA_D1_MISO2 35 DQ1
V14 FPGA_D2_MISO3 38 DQ2
U5 FLASH_D3 40 DQ3
V5 FLASH_D4 44 DQ4
R3 FLASH_D5 46 DQ5
T3 FLASH_D6 49 DQ6
R5 FLASH_D7 51 DQ7
M16 FLASH_WE_B 55 WE_B
L18 FLASH_OE_B 54 OE_B
Table 1-7: BPI Memory Connections (Cont’d)
FPGA U1 Pin Schematic Netname
BPI Memory U10
Pin Number Pin