Xilinx SP601 Hardware UG518 - Manual (Page 51)

SP601 Hardware User Guide www.xilinx.com 51
UG518 (v1.1) August 19, 2009
Appendix D
SP601 Master UCF
The UCF template is provided for designs that target the SP601. Net names provided in the
constraints below correlate with net names on the SP601 rev. C schematic. On identifying
the appropriate pins, the net names below should be replaced with net names in the user
RTL. See the
Constraints Guide for more information.
NET "CPU_RESET" LOC = "N4";
NET "DDR2_A0" LOC = "J7";
NET "DDR2_A1" LOC = "J6";
NET "DDR2_A2" LOC = "H5";
NET "DDR2_A3" LOC = "L7";
NET "DDR2_A4" LOC = "F3";
NET "DDR2_A5" LOC = "H4";
NET "DDR2_A6" LOC = "H3";
NET "DDR2_A7" LOC = "H6";
NET "DDR2_A8" LOC = "D2";
NET "DDR2_A9" LOC = "D1";
NET "DDR2_A10" LOC = "F4";
NET "DDR2_A11" LOC = "D3";
NET "DDR2_A12" LOC = "G6";
NET "DDR2_BA0" LOC = "F2";
NET "DDR2_BA1" LOC = "F1";
NET "DDR2_BA2" LOC = "E1";
NET "DDR2_CAS_B" LOC = "K5";
NET "DDR2_CKE" LOC = "H7";
NET "DDR2_CLK_N" LOC = "G1";
NET "DDR2_CLK_P" LOC = "G3";
NET "DDR2_DQ0" LOC = "L2";
NET "DDR2_DQ1" LOC = "L1";
NET "DDR2_DQ2" LOC = "K2";
NET "DDR2_DQ3" LOC = "K1";
NET "DDR2_DQ4" LOC = "H2";
NET "DDR2_DQ5" LOC = "H1";
NET "DDR2_DQ6" LOC = "J3";
NET "DDR2_DQ7" LOC = "J1";
NET "DDR2_DQ8" LOC = "M3";
NET "DDR2_DQ9" LOC = "M1";
NET "DDR2_DQ10" LOC = "N2";
NET "DDR2_DQ11" LOC = "N1";
NET "DDR2_DQ12" LOC = "T2";
NET "DDR2_DQ13" LOC = "T1";
NET "DDR2_DQ14" LOC = "U2";
NET "DDR2_DQ15" LOC = "U1";
NET "DDR2_LDM" LOC = "K3";
NET "DDR2_LDQS_N" LOC = "L3";