Rainbow Electronics MAX3107 - Manual (Page 32)

32 _____________________________________________________________________________________
MAX3107
SPI/I
2
C UART with 128-Word FIFOs
and Internal Oscillator
Bit 7: EchoSuprs
Set the EchoSuprs bit high so that the MAX3107’s receiver gates any data it receives when its transmitter is busy
transmitting. In half-duplex communication (like IrDA and RS-485) this allows blocking of the locally echoed data. The
receiver can block data for an extended time after the transmitter ceases transmission by programming a hold time in
HDplxDelay[3:0] bits.
Bit 6: MultiDrop
Set the MultiDrop bit high to enable the 9-bit multidrop mode. If this bit is set, parity checking is not performed by the
receiver and parity generation is not done by the transmitter. The parity error bit, LSR[2], has a different meaning in
this case. The parity error bit represents the 9th bit (address/data indication) that is received with each 9-bit character.
Bit 5: Loopback
Set the Loopback bit high to enable internal local loopback mode. This internally connects TX to RX and also RTS/
CLKOUT to CTS. In local loopback mode, the TX output and the RX output are disconnected from the internal transmit-
ter and receiver. The TX output is in three-state. The RTS output remains connected to the internal logic and reflects the
logic state programmed in LCR[7]. The CTS input is disconnected from RTS and the internal logic. CTS thus remains
in a high-impedance state.
Bit 4: SpecialChr
The SpecialChr bit enables special character detection. The receiver can detect up to four special characters, as
selected in FlowCtrl:[5:4] and defined in the XON1, XON2, XOFF1 and/or XOFF2 registers, possibly in combination with
GPIO_ inputs, enabled through FlowCtrl[2]: GPIAddr. When a special character is received it is put into the RxFIFO and
a special character detect interrupt ISR[1] is generated.
Special character detection can be used in addition to Auto XON/XOFF flow control, if enabled through FlowCtrl[3]. In
this case XON/OFF flow control is then limited to single character XON and XOFF and only two special characters can
then be defined (in XON2 and XOFF2).
Bit 3: RxEmtyInv
The RxEmtyInv bit inverts the meaning of the receiver empty interrupt: ISR[6]: RxEmtyInt. If RxEmtyInv is set low (default
state), the ISR[6] interrupt is generated when the receive FIFO is empty. If the RxEmtyInv is set high, the ISR[6] interrupt
is generated when the receive FIFO contains at least one character (i.e., is not empty).
Bit 2: RxTrigInv
The RxTrigInv bit inverts the meaning of the RxFIFO triggering. When set, an ISR[3]: RFifoTrigInt is generated when
the RxFIFO is emptied to the trigger level: FIFOTrgLvl[7:4]. If the RxTrgInv bit is low (default state), the ISR[3] interrupt
is generated when the RxFIFO fill level that starts from a level below FIFOTrgLvl[7:4] is filled up to the trigger level
programmed into FIFOTrgLvl[7:4].
Bit 1: FIFORst
Set the FIFORst bit high to clear both the receive and transmit FIFOs of all data contents. After the FIFO reset, the
FIFORst bit must then be set back to 0 to continue normal operation.
Bit 0: RST
Set the RST bit high to reset the MAX3107. The SPI/I
2 C bus stays active during this reset, therefore, communication
with the MAX3107 is possible. All register bits are reset to their reset state and all FIFOs are cleared.
Once set high, the RST bit must be cleared by writing a 0 to RST.
MODE2 Register
ADDRESS: 0x0A
MODE: R/W
BIT 7 6 5 4 3 2 1 0
NAME EchoSuprs MultiDrop Loopback SpecialChr RxEmtyInv RxTrigInv FIFORst RST
RESET 0 0 0 0 0 0 0 0