Rainbow Electronics MAX3107 - Manual (Page 9)

_______________________________________________________________________________________ 9
MAX3107
SPI/I
2
C UART with 128-Word FIFOs
and Internal Oscillator
AC ELECTRICAL CHARACTERISTICS (continued)
(V A = +2.35V to +3.6V, V L = +1.71V to +3.6V, V EXT = +1.71V to +3.6V, T A = -40NC to +85NC, unless otherwise noted. Typical values
are at V A = +2.8V, V L = +1.8V, V EXT = +2.5V, T A = +25NC.) (Note 2)
Note 2: All devices are production tested at T A = +25NC. Specifications over temperature are guaranteed by design.
Note 3: Not production tested. Guaranteed by design.
Note 4: When V
18 is powered by an external voltage regulator, the external power supply must have current capability above or
equal to I 18 .
Note 5: C B is the total capacitance of either the clock or data line of the synchronous bus in pF.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Data Setup Time t SU:DAT
Standard mode 250
ns
Fast mode 100
Setup Time for Repeated START
(Sr) Condition
t SU:STA
Standard mode 4.7
F s
Fast mode 0.6
Rise Time of SDA and SCL
Signals Receiving
t R
Standard mode (0.3 x V
L
to 0.7 x V
L
)
(Note 5)
20 +
0.1C B
1000
ns
Fast mode (0.3 x V L to 0.7 x V L ) (Note 5)
20 +
0.1C B
300
Fall Time of SDA and SCL
Signals
t F
Standard mode (0.7 x V L to 0.3 x V L )
(Note 5)
20 +
0.1C B
300
ns
Fast mode (0.7 x V L to 0.3 x V L ) (Note 5)
20 +
0.1C B
300
Setup Time for STOP (P)
Condition
t SU:STO
Standard mode 4.7
F s
Fast mode 0.6
Capacitive Load for SDA and
SCL (Note 3)
C B
Standard mode 400
pF
Fast mode 400
I/O Capacitance (SCL, SDA) C I/O 10 pF
Pulse Width of Spike
Suppressed
t
SP
50 ns
SPI BUS: TIMING CHARACTERISTICS (see Figure 2)
SCLK Clock Period
t CH+CL 38.4 ns
SCLK Pulse-Width High t CH 16 ns
SCLK Pulse-Width Low t CL 16 ns
CS Fall to SCLK Rise Time t
CSS
0 ns
DIN Hold Time t DH 3 ns
DIN Setup Time t DS 5 ns
Output Data Propagation Delay t DO 20 ns
DOUT Rise and Fall Times t FT 10 ns
CS Hold Time t CSH 32 ns