Rainbow Electronics MAX1386 - Manual (Page 18)

MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I
2 C/SPI Interface
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Detailed Description
The MAX1385/MAX1386 set and control bias conditions
for dual RF LDMOS power devices found in cellular
base stations. Each device includes a high-side cur-
rent-sense amplifier with programmable gains of 2, 10,
and 25 to monitor the LDMOS drain current over the
20mA to 5A range. Two external diode-connected tran-
sistors monitor the LDMOS temperatures while an inter-
nal temperature sensor measures the local die
temperature of the MAX1385/MAX1386. A 12-bit ADC
converts the programmable-gain amplifier (PGA) out-
puts, external/internal temperature readings, and two
auxiliary inputs.
The two gate-drive channels, each consisting of 8-bit
coarse and 10-bit fine DACs and a gate-drive amplifier,
generate a positive gate voltage to bias the LDMOS
devices. The MAX1385 includes a gate-drive amplifier
with a gain of 2 and the MAX1386 gate-drive amplifier
provides a gain of 4. The 8-bit coarse and 10-bit fine
DACs allow up to 18 bits of resolution. The MAX1385/
MAX1386 include autocalibration modes to minimize
error over time, temperature, and supply voltage.
The MAX1385/MAX1386 feature an I 2 C-/SPI-compatible
serial interface. Both devices operate from a 4.75V to
5.25V analog supply (3.2mA supply current), a 2.7V to
5.25V digital supply (3.1mA supply current), and a 4.75V
to 11.0V gate-drive supply (4.5mA supply current).
Power-On Reset
On power-up, the MAX1385/MAX1386 are in full power-
down mode (see the
SSHUT (Write) section). To change
to normal power mode, write two commands to the
Software Shutdown register. The first command sets
FULLPD to 0 (other bits in the Software Shutdown register
are ignored). A second command is needed to activate
any internal blocks. The recommended sequence of com-
mands to ensure reliable startup following the application
of power, is given in the
Appendix: Recommended
Power-Up Code Sequence section.
ADC Description
The MAX1385/MAX1386 ADC uses a fully differential
successive approximation register (SAR) conversion
technique and on-chip track-and-hold (T/H) circuitry to
convert temperature and voltage signals into 12-bit dig-
ital results. The analog inputs accept single-ended
input signals. Single-ended signals are converted using
a unipolar transfer function. See the ADC transfer func-
tion of Figure 25 for more information.
The internal ADC block converts the results of the die
temperature, remote diode temperature readings,
PGAOUT1, PGAOUT2, ADCIN1, or ADCIN2 voltages
according to which bits are set in the ADC Conversion
register (see the
ADCCON (Write) section). The results
of the conversions are written to FIFO memory. The
FIFO holds up to 15 words (each word is 16 bits) with
channel tags to indicate which channel the 12-bit data
comes from. The FIFO indicates an overflow condition
and an underflow condition (read of an empty FIFO) by
the Flag register (see the
RDFLAG (Read) section) and
channel tags. The FIFO always stores the most recent
conversion results and allows the oldest data to be
overwritten. Read the latest result stored in the FIFO by
sending the appropriate read command byte (see the
FIFO (Read) section).
Read the data stored in the FIFO through the FIFO
Read register. The
FIFO (Read) section details which
channel is being read and whether the FIFO has over-
flowed.
Analog-to-Digital Conversion Scheduling
The MAX1385/MAX1386 ADC multiplexer scans select-
ed inputs in the order shown in Table 1. The ADC multi-
plexer skips over the items that are not selected in the
Analog-to-Digital Conversion register. When writing a
conversion command before a conversion is complete,
the pending conversion may be canceled. In addition,
using the serial interface while the ADC is converting
may degrade the performance of the ADC.
ADC Clock Modes
The MAX1385/MAX1386 offer three different conver-
sion/acquisition modes (known as clock modes) selec-
table through the Device Configuration register (see the
DCFIG (Read/Write) section). Clock Mode 10 is
reserved and cannot be used. For conversion/acquisi-
tion examples and timing diagrams, see the
Applications Information section.
If the analog-to-digital conversion requires the internal
reference (temperature measurement or voltage mea-
surement with internal reference selected) and the ref-
erence has not been previously forced on, the device
inserts a worst-case delay of 81µs, for the reference to
settle, before commencing the analog-to-digital conver-
sion. The reference remains powered up while there are
pending conversions. If the reference is not forced on,
it automatically powers down at the end of a scan or
when CONCONV in the Analog-to-Digital Conversion
register is set back to 0.