C/spi interface, Appendix: recommended power-up code sequence – Rainbow Electronics MAX1386 User Manual

Page 52

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MAX1385/MAX1386

Dual RF LDMOS Bias Controllers
with I

2

C/SPI Interface

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

52 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2009 Maxim Integrated Products

Maxim is a registered trademark of Maxim Integrated Products, Inc.

Appendix: Recommended

Power-Up Code Sequence

The following section shows the recommended startup
code for the MAX1385. This code ensures clean startup

of the part, irrespective of power-supply ramp speed
and starts the device regulating to 312.5mV on both
channels. Change the THRUDAC writes to change the
voltage across the sense resistor. Note it should be run
after the power supplies have stabilized.

*Double reset. This ensures that the internal ROM is reset correctly after power-up and that the ROM data is latched correctly irre-
spective of power-supply ramp speed.

REGISTER

MNEMONIC

REGISTER

ADDRESS (hex)

CODE

WRITTEN

NOTES

SHUT

0x64

0x0080

Removes the global power.

SHUT

0x64

0x0080

Powers up all parts of the MAX1385 and forces the internal reference to
remain powered. The internal oscillator is required for the subsequent
reset command.

SCLR

0x68

0x0100

Arms the full reset.

SCLR

0x68

0x0200

Completes the full reset.

SCLR

0x68

0x0100

Arms the full reset.*

SCLR

0x68

0x0200

Completes the full reset.*

SHUT

0x64

0x0080

Removes the global power.

SHUT

0x64

0x0080

Powers up all parts of the MAX1385 and forces the internal reference to
remain powered. The internal oscillator is required for the subsequent
reset command.

DCFIG

0x30

0x000A

Selects internal references for both DAC and ADC.

PGACAL

0x4E

0x0002

Runs autocalibration on both PGA channels to set the input referred
offset to < 50µV. Busy goes low after approximately 30ms and then the
V

GATE

DACs can be set.

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