Rainbow Electronics MAX1386 - Manual (Page 29)

MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I 2 C/SPI Interface
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Use the following equation to find the required thresh-
old code for a specified threshold current:
where I DRAIN is the current threshold in amperes,
R SENSE is the sense resistor, Av
PGA
is the voltage gain
of the PGA, V REFADC is the ADC reference voltage, and
I THRESH is the resulting threshold register value
in decimal.
DCFIG (Read/Write)
Select PGA gain settings, clock modes, and DAC and
ADC reference modes by sending the appropriate write
command byte followed by data bits D15–D0 (see
Table 7). Bits D15–D10 are don’t care. Read the Device
Configuration register by sending the appropriate read
command byte. Program PG2SET1 and PG2SET0 to set
channel 2’s current-sense amplifier gain (see Table 7a).
Program PG1SET1 and PG1SET0 to set channel 1’s
current-sense amplifier gain (see Table 7a). Set
CKSEL1 and CKSEL0 to determine the conversion and
acquisition timing clock modes (see Table 7b). See the
ADC Clock Modes section for a functional description
of each clock mode. Set REFADC1 and REFADC0 to
select external/internal reference for the ADC (see
Table 7c). Set REFDAC1 and REFDAC0 to select exter-
nal/internal reference for both DACs (see Table 7d).
When mode 11 is selected, the external capacitor that
is connected to the REFADC is charged by a resistor
with a typical value of 400kΩ. This time constant needs
to be allowed for powering up the reference. Avoid
leakage paths to REFADC.
ALMSCFG (Read/Write)
The Software Alarm Configuration register controls the
behavior of outputs SAFE1, SAFE2, and ALARM. Write
to the Software Alarm Configuration register by sending
the appropriate write command byte followed by data
bits D15–D0 (see Table 8). Bits D15–D12 are don’t
care. Read the Software Alarm Configuration register
by sending the appropriate command byte.
Set ALMSCLR to 1 to immediately set all temperature/
current threshold registers to their POR state. In addi-
tion, temperature-/current-related bits of the Flag regis-
ter are also reset to their POR state. The ALMSCLR
resets to 0 immediately after a write. Set ALARMCMP to
1 to enable output-comparator mode for ALARM and to
0 to enable output-interrupt mode for ALARM (see the
I I R Av
V
THRESH DRAIN SENSE PGA
REFADC
= Ч Ч Ч
4096
D15 D14 D13 D12
D11
(MSB)
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
D0
(LSB)
POR X X X X 1 0 0 0 0 0 0 0 0 0 0 0
Bit Value
(°C)
X X X X -256 +128 +64 +32 +16 +8 +4 +2 +1 +0.5 +0.25 +0.125
Table 4. TL1 and TL2 (Read/Write)
X = Don’t care.
D15 D14 D13 D12
D11
(MSB)
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
D0
(LSB)
POR X X X X 1 1 1 1 1 1 1 1 1 1 1 1
Bit Value X X X X — — — — — — — — — — — —
Table 5. IH1 and IH2 (Read/Write)
X = Don’t care.
D15 D14 D13 D12
D11
(MSB)
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
D0
(LSB)
POR X X X X 0 0 0 0 0 0 0 0 0 0 0 0
Bit Value X X X X — — — — — — — — — — — —
Table 6. IL1 and IL2 (Read/Write)
X = Don’t care.