Rainbow Electronics MAX1386 - Manual (Page 31)

MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I 2 C/SPI Interface
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DAC input register is transferred to the appropriate DAC
output register. Automatic calibration of the high wiper is
initiated if the HCAL bit in the DAC input register is set to
1 when the appropriate LDAC command is issued.
LOWIPE1 and LOWIPE2 (Read/Write)
Write to the Coarse DAC1/DAC2 Low Wiper Input regis-
ter by sending the appropriate command byte followed
by data bits D15–D0 (see Table 10). Bits D14–D8 are
don’t care. Read the Coarse DAC1/DAC2 Low Wiper
Input register by sending the appropriate read com-
mand byte. The DAC output is not updated until an
LDAC command is issued, at which point the DAC
input register is transferred to the appropriate DAC out-
put register. Automatic calibration of the low wiper is
initiated if the LCAL bit in the DAC input register is set
to 1 when the appropriate LDAC command is issued.
FINECAL1 and FINECAL2 (Write)
Write to the Fine DAC1/DAC2 Input register with auto-
calibration by sending the appropriate write command
byte followed by data bits D15–D0 (see Table 11). Bits
D15–D10 are don’t care. A write to these registers trig-
gers the autocalibration but does not automatically
update the output of the DAC. Write to the Software
LDAC register (LDAC) to transfer the Fine DAC Input
register contents to the Fine DAC Output register,
thereby updating the output of the DAC. POR contents
for these registers are all zeros. Read the DAC input
register values written to Fine DAC1 and DAC2 Input
registers through the Fine DAC1/DAC2 Input Read reg-
ister. These read registers contain the latest user-write
to any Fine DAC1 or Fine DAC2 Input Read register
and do not contain autocalibration-corrected values.
PGACAL (Write)
Write to the PGA Calibration Control register to calibrate
PGA1 and PGA2 internal amplifiers. Write to the PGA
Calibration Control register by sending the appropriate
write command byte followed by data bits D15–D0 (see
Table 12). Bits D15–D8 are reserved and must be set to
0. Bits D7–D3 are don’t care. Set FIRSTB to 1 to enable
tracking-calibration mode, and to 0 to enable acquisi-
tion-calibration mode.
During an offset calibration trial, for either mode, the
corresponding PGAOUT_ is put into hold, which pro-
duces a pedestal error for 67µs typically and BUSY is
set to 1. In acquisition mode, the calibration routine
operates continuously, first on channel 1 and then on
channel 2, until the channel-input offset voltage error
has been reduced to within 50µV. The time taken for
both channels to complete acquisition depends upon
the initial channel offset voltage error but should never
be longer than 112ms. In tracking mode, a pair of offset
calibration trials, first on channel 1 and then on channel
2, are made each time DOCAL is set to 1 or every 20ms
if the SELFTIME bit is set to 1. To reject noise, the offset
trim DAC code (not shown in the
Functional Diagram )
only increments or decrements after the results of 16
calibration trials have been averaged.
Set FIRSTB to 0 and DOCAL to 1 to initiate an acquisi-
tion calibration. Acquisition must be done before track-
ing the first time a PGA calibration is commanded. Set
FIRSTB to 1, DOCAL to 1, and SELFTIME to 0 to trigger
an offset calibration trial on PGA1 and PGA2. At the
end of the routine, DOCAL returns to 0. Set FIRSTB to
1, DOCAL to 1 (optional to trigger calibration once
immediately before SELFTIME starts periodic calibra-
tions), and SELFTIME to 1, just once, to trigger periodic
offset-calibration trials (approximately every 20ms). Set
SELFTIME to 0 to halt the periodic calibration.
FINE1 and FINE2 (Write)
Write to the Fine DAC1/DAC2 Input register without auto-
calibration by sending the appropriate write command
byte followed by data bits D15–D0 (see Table 13). Bits
D15–D10 are don’t care. A write to these registers does
not trigger the autocalibration and does not automatically
update the output of the DAC. Write to the Software
LDAC register (LDAC) to transfer the DAC input register
contents to the Fine DAC Output register, thereby updat-
ing the output of the fine DAC. POR contents for these
registers are all zeros. Read the DAC input register val-
ues written to Fine DAC1 and DAC2 Input registers
through the Fine DAC1/DAC2 Input Read register. These
read registers contain the latest user-write to any Fine
DAC1 or Fine DAC2 Input Read register and do not con-
tain autocalibration corrected values.
FINETHRU1 and FINETHRU2 (Write)
Write to the Fine DAC1/DAC2 Write-Through Input reg-
ister without autocalibration by sending the appropriate
write command byte followed by data bits D15–D0 (see
REFDAC1 REFDAC0 DESCRIPTION
0 X
External. Bypass REFDAC with a
0.1µF capacitor to AGND.
1 0
Internal. Leave REFDAC
unconnected.
1 1
Internal. Connect a 0.1µF capacitor
to REFDAC for extra decoupling
and better noise performance.
Table 7d. DAC Reference Selection
X = Don’t care.